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From: David Daney <ddaney@caviumnetworks.com>
To: post@pfrst.de, Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: Re: cacheflush system call-MIPS
Date: Tue, 17 Feb 2009 09:06:32 -0800	[thread overview]
Message-ID: <499AEE98.1010908@caviumnetworks.com> (raw)
In-Reply-To: <Pine.LNX.4.58.0902150312460.459@Indigo2.Peter>

peter fuerst wrote:
>> Why does it need that flush?
> 
> To prepare the update-area (in the Shadow-FB) for DMA to RE.
> 
> 

And on systems where the root frame buffer is directly manipulated by 
the CPU, the video system is continually using DMA to refresh the 
display.  A cache flush can be required to eliminate transient visual 
glitches.

David Daney



> kind regards
> 
> 
> 
> On Fri, 13 Feb 2009, Ralf Baechle wrote:
> 
>> Date: Fri, 13 Feb 2009 23:56:03 +0000
>> From: Ralf Baechle <ralf@linux-mips.org>
>> To: peter fuerst <post@pfrst.de>
>> Cc: naresh kamboju <naresh.kernel@gmail.com>, linux-mips@linux-mips.org
>> Subject: Re: cacheflush system call-MIPS
>>
>> On Sat, Feb 14, 2009 at 12:50:46AM +0100, peter fuerst wrote:
>>
>>> there is one more good reason to ... : the Impact Xserver needs to do
>>> a cacheflush(a,w,DCACHE) as part of the refresh-sequence.
>>> And hence requires a sys_cacheflush, let's say, more conforming to the
>>> man-page (or some disgusting new ioctl in the Impact kernel-driver to
>>> do an equivalent operation ;-)
>> Why does it need that flush?
>>
>>   Ralf
>>
>>
> 
> 

  reply	other threads:[~2009-02-17 17:07 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-02-10 15:16 cacheflush system call-MIPS naresh kamboju
2009-02-11 13:16 ` Ralf Baechle
2009-02-13 23:50   ` peter fuerst
2009-02-13 23:56     ` Ralf Baechle
2009-02-15  2:20       ` peter fuerst
2009-02-17 17:06         ` David Daney [this message]
2009-02-17 19:45           ` Eugene Surovegin
2009-02-17 20:50             ` David VomLehn (dvomlehn)
2009-02-17 20:50               ` David VomLehn (dvomlehn)

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