[PATCH v5 00/12] MIPS performance event support v5

[PATCH v5 00/12] MIPS performance event support v5

[Deng-Cheng Zhu]

The patches 1~7 (can be applied/built/tested independently) of this
package implement the low-level logic for the Linux performance counter
subsystem (Perf-events) on MIPS, which enables the collection of all sorts
of HW/SW performance events based on per-CPU or per-task. For more
information, please refer to tools/perf/Documentation/perf.txt.

And No. 8~12 make Oprofile use Perf-events framework as backend. This
effort makes the bug-fixes shared by different pmu users/clients (for now,
Oprofile & Perf-events), and make them coexist in the system without
locking issues, and make their results comparable.

The whole patchset was tested on the Malta-R board. 24K/34K/74K/1004K
cores and SMVP/UP kernels have been basically tested. Welcome any more
tests against these cores for Perf-events and all mipsxx CPUs for
Oprofile.

To test the functionality of Perf-event, you may want to compile the tool
"perf" for your MIPS platform. You can refer to the following URL:
http://www.linux-mips.org/archives/linux-mips/2010-04/msg00158.html

Please note: Before that patch is accepted, you can choose a "specific"
rmb() which is suitable for your platform -- an example is provided in
the description of that patch.

You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile
for your libs, includes, etc.

In case you encounter the boot failure in SMVP kernel on multi-threading
CPUs, you may take a look at:
http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020

Note:
1) To support mipsxx CPUs other than 24K/34K/74K/1004K, the corresponding
general event map, cache event map and raw event macros need to be added.
Please refer to init_hw_perf_events() for more info. Please note that,
even before this is done, Oprofile with the new framework can still work
on *ALL* mipsxx CPUs. For those CPUs not yet having "precise" raw event
implementation (refer to patch #7), the unchecked raw events are used.
2) To support other CPUs which have different PMU than mipsxx, such as
RM9000 and LOONGSON2, additional files perf_event_$cpu.c need to be
created.

So, the patches 1~7 can be reviewed and applied (if OK, hope so) without
affecting the existing Oprofile and other parts --- only a new kernel
facility is brought in :-) And the patches 8~12 can be applied after
perf_event_rm9000.c and perf_event_loongson2.c are added in, because 8~12
removed all the old Oprofile interfaces and replaced with new ones, which
will call into the rm9000/loongson2 Perf-events backend on corresponding
CPUs.

CHANGES:
-----------------------------
v5 - v4:
- splitting up Perf-events patches (v4 patches 1~4 are now splitted into
v5 patches 1~7) for easier review.
- adding more info into the description of patches (especially how to test
this patchset).
- simplifying the 2 small functions mipspmu_get_pmu_id() and
mipspmu_get_max_events().
v4 - v3:
- placing the variable save_perf_irq properly (issue found by Wu Zhangjin)
- the patches 5~9 make Oprofile use Perf-events framework as backend.
v3 - v2:
- adding 1004K core support.
- slightly adjusting the code structure.
- adding more comments in the code.
- fixing some small coding style issues.
v2 - v1:
- Adjusting code structure as suggested by Wu Zhangjin. With this change,
hardware performance event support for loongson2 and rm9000 can be
conveniently implemented by adding and including new files like
perf_event_loongson2.c; Oprofile and Perf for MIPS are now sharing pmu.h;
Naming changes were made to some functions.
- Fixing the generic atomic64 issue reported by David Daney. Currently,
32bit kernel is using the generic version from lib. When Ralf Baechle's
common atomic64 version is ready, this may change.
- Adding raw event support. For more details, please refer to the code
comments for mipsxx_pmu_map_raw_event().
- Adding new software events - PERF_COUNT_SW_ALIGNMENT_FAULTS and
PERF_COUNT_SW_EMULATION_FAULTS.
- Fixing some small bugs.
- Adding new comments for the code.
- Making some code style changes.
v1:
- Using generic atomic64 operations from lib.
- SMVP/UP kernels are supported (not for SMTC).
- 24K/34K/74K cores are implemented.
- Currently working when Oprofile is _not_ available.
- Minimal software perf events are supported.
-----------------------------

Deng-Cheng Zhu (12):
  MIPS/Oprofile: extract PMU defines/helper functions for sharing
  MIPS: use generic atomic64 in non-64bit kernels
  MIPS: add support for software performance events
  MIPS: add support for hardware performance events (skeleton)
  MIPS/Perf-events: add callchain support
  MIPS: add support for hardware performance events (mipsxx)
  MIPS/Perf-events: add raw event support for mipsxx 24K/34K/74K/1004K
  MIPS: move mipsxx pmu helper functions to Perf-events
  MIPS/Perf-events: replace pmu names with numeric IDs
  MIPS/Perf-events: allow modules to get pmu number of counters
  MIPS/Oprofile: use Perf-events framework as backend
  MIPS/Oprofile: remove old files and update Kconfig/Makefile

 arch/mips/Kconfig                       |   13 +-
 arch/mips/include/asm/atomic.h          |    4 +
 arch/mips/include/asm/perf_event.h      |   28 +
 arch/mips/include/asm/pmu.h             |  119 ++++
 arch/mips/kernel/Makefile               |    2 +
 arch/mips/kernel/perf_event.c           |  647 +++++++++++++++++++
 arch/mips/kernel/perf_event_mipsxx.c    | 1039 +++++++++++++++++++++++++++++++
 arch/mips/kernel/traps.c                |   18 +-
 arch/mips/kernel/unaligned.c            |    5 +
 arch/mips/math-emu/cp1emu.c             |    3 +
 arch/mips/mm/fault.c                    |   11 +-
 arch/mips/oprofile/Makefile             |    7 -
 arch/mips/oprofile/common.c             |  237 ++++++--
 arch/mips/oprofile/op_impl.h            |   39 --
 arch/mips/oprofile/op_model_loongson2.c |  155 -----
 arch/mips/oprofile/op_model_mipsxx.c    |  397 ------------
 arch/mips/oprofile/op_model_rm9000.c    |  138 ----
 17 files changed, 2061 insertions(+), 801 deletions(-)
 create mode 100644 arch/mips/include/asm/perf_event.h
 create mode 100644 arch/mips/include/asm/pmu.h
 create mode 100644 arch/mips/kernel/perf_event.c
 create mode 100644 arch/mips/kernel/perf_event_mipsxx.c
 delete mode 100644 arch/mips/oprofile/op_impl.h
 delete mode 100644 arch/mips/oprofile/op_model_loongson2.c
 delete mode 100644 arch/mips/oprofile/op_model_mipsxx.c
 delete mode 100644 arch/mips/oprofile/op_model_rm9000.c

[PATCH v5 01/12] MIPS/Oprofile: extract PMU defines/helper functions for sharing

[Deng-Cheng Zhu]

Moving performance counter/control defines/helper functions into a single
header file, so that software using the MIPS PMU can share the code.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/include/asm/pmu.h             |  236 +++++++++++++++++++++++++++++++
 arch/mips/oprofile/op_model_loongson2.c |   18 +---
 arch/mips/oprofile/op_model_mipsxx.c    |  164 +---------------------
 arch/mips/oprofile/op_model_rm9000.c    |   16 +--
 4 files changed, 240 insertions(+), 194 deletions(-)
 create mode 100644 arch/mips/include/asm/pmu.h

diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
new file mode 100644
index 0000000..162b24f
--- /dev/null
+++ b/arch/mips/include/asm/pmu.h
@@ -0,0 +1,236 @@
+/*
+ * linux/arch/mips/include/asm/pmu.h
+ *
+ * Copyright (C) 2004, 05, 06 by Ralf Baechle
+ * Copyright (C) 2005 by MIPS Technologies, Inc.
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Yanhua <yanh@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu
+ *
+ * This file is shared by Oprofile and Perf. It is also shared across the
+ * Oprofile implementation for different MIPS CPUs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MIPS_PMU_H__
+#define __MIPS_PMU_H__
+
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
+    defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
+
+#define M_CONFIG1_PC	(1 << 4)
+
+#define M_PERFCTL_EXL			(1UL      <<  0)
+#define M_PERFCTL_KERNEL		(1UL      <<  1)
+#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)
+#define M_PERFCTL_USER			(1UL      <<  3)
+#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)
+#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
+#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
+#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
+#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
+#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
+#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
+#define M_PERFCTL_WIDE			(1UL      << 30)
+#define M_PERFCTL_MORE			(1UL      << 31)
+
+#define M_COUNTER_OVERFLOW		(1UL      << 31)
+
+#ifdef CONFIG_MIPS_MT_SMP
+static int cpu_has_mipsmt_pertccounters;
+#define WHAT		(M_TC_EN_VPE | \
+			M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
+/*
+ * FIXME: For VSMP, vpe_id() is redefined for Perf, because
+ * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. WHAT is not
+ * redefined because Perf does not use it.
+ */
+#if defined(CONFIG_HW_PERF_EVENTS)
+#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
+			0 : smp_processor_id())
+#else
+#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
+			0 : cpu_data[smp_processor_id()].vpe_id)
+#endif
+/*
+ * The number of bits to shift to convert between counters per core and
+ * counters per VPE.  There is no reasonable interface atm to obtain the
+ * number of VPEs used by Linux and in the 34K this number is fixed to two
+ * anyways so we hardcore a few things here for the moment.  The way it's
+ * done here will ensure that oprofile VSMP kernel will run right on a lesser
+ * core like a 24K also or with maxcpus=1.
+ */
+static inline unsigned int vpe_shift(void)
+{
+	if (num_possible_cpus() > 1)
+		return 1;
+
+	return 0;
+}
+#else
+#define WHAT		0
+#define vpe_id()	0
+static inline unsigned int vpe_shift(void)
+{
+	return 0;
+}
+#endif
+
+static inline unsigned int
+counters_total_to_per_cpu(unsigned int counters)
+{
+	return counters >> vpe_shift();
+}
+
+static inline unsigned int
+counters_per_cpu_to_total(unsigned int counters)
+{
+	return counters << vpe_shift();
+}
+
+#define __define_perf_accessors(r, n, np)				\
+									\
+static inline unsigned int r_c0_ ## r ## n(void)			\
+{									\
+	unsigned int cpu = vpe_id();					\
+									\
+	switch (cpu) {							\
+	case 0:								\
+		return read_c0_ ## r ## n();				\
+	case 1:								\
+		return read_c0_ ## r ## np();				\
+	default:							\
+		BUG();							\
+	}								\
+	return 0;							\
+}									\
+									\
+static inline void w_c0_ ## r ## n(unsigned int value)			\
+{									\
+	unsigned int cpu = vpe_id();					\
+									\
+	switch (cpu) {							\
+	case 0:								\
+		write_c0_ ## r ## n(value);				\
+		return;							\
+	case 1:								\
+		write_c0_ ## r ## np(value);				\
+		return;							\
+	default:							\
+		BUG();							\
+	}								\
+	return;								\
+}									\
+
+__define_perf_accessors(perfcntr, 0, 2)
+__define_perf_accessors(perfcntr, 1, 3)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
+
+__define_perf_accessors(perfctrl, 0, 2)
+__define_perf_accessors(perfctrl, 1, 3)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
+
+static inline int __n_counters(void)
+{
+	if (!(read_c0_config1() & M_CONFIG1_PC))
+		return 0;
+	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
+		return 1;
+	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
+		return 2;
+	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
+		return 3;
+
+	return 4;
+}
+
+static inline int n_counters(void)
+{
+	int counters;
+
+	switch (current_cpu_type()) {
+	case CPU_R10000:
+		counters = 2;
+		break;
+
+	case CPU_R12000:
+	case CPU_R14000:
+		counters = 4;
+		break;
+
+	default:
+		counters = __n_counters();
+	}
+
+	return counters;
+}
+
+static void reset_counters(void *arg)
+{
+	int counters = (int)(long)arg;
+	switch (counters) {
+	case 4:
+		w_c0_perfctrl3(0);
+		w_c0_perfcntr3(0);
+	case 3:
+		w_c0_perfctrl2(0);
+		w_c0_perfcntr2(0);
+	case 2:
+		w_c0_perfctrl1(0);
+		w_c0_perfcntr1(0);
+	case 1:
+		w_c0_perfctrl0(0);
+		w_c0_perfcntr0(0);
+	}
+}
+
+/* Used by Perf */
+#define MIPS_MAX_HWEVENTS 4
+
+#elif defined(CONFIG_CPU_RM9000)
+
+#define RM9K_COUNTER1_EVENT(event)	((event) << 0)
+#define RM9K_COUNTER1_SUPERVISOR	(1ULL    <<  7)
+#define RM9K_COUNTER1_KERNEL		(1ULL    <<  8)
+#define RM9K_COUNTER1_USER		(1ULL    <<  9)
+#define RM9K_COUNTER1_ENABLE		(1ULL    << 10)
+#define RM9K_COUNTER1_OVERFLOW		(1ULL    << 15)
+
+#define RM9K_COUNTER2_EVENT(event)	((event) << 16)
+#define RM9K_COUNTER2_SUPERVISOR	(1ULL    << 23)
+#define RM9K_COUNTER2_KERNEL		(1ULL    << 24)
+#define RM9K_COUNTER2_USER		(1ULL    << 25)
+#define RM9K_COUNTER2_ENABLE		(1ULL    << 26)
+#define RM9K_COUNTER2_OVERFLOW		(1ULL    << 31)
+
+extern unsigned int rm9000_perfcount_irq;
+
+#elif defined(CONFIG_CPU_LOONGSON2)
+
+#define LOONGSON2_CPU_TYPE	"mips/loongson2"
+
+#define LOONGSON2_PERFCNT_OVERFLOW		(1ULL   << 31)
+
+#define LOONGSON2_PERFCTRL_EXL			(1UL	<<  0)
+#define LOONGSON2_PERFCTRL_KERNEL		(1UL    <<  1)
+#define LOONGSON2_PERFCTRL_SUPERVISOR		(1UL    <<  2)
+#define LOONGSON2_PERFCTRL_USER			(1UL    <<  3)
+#define LOONGSON2_PERFCTRL_ENABLE		(1UL    <<  4)
+#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
+	(((event) & 0x0f) << ((idx) ? 9 : 5))
+
+#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
+#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
+#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
+#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
+
+#endif /* CONFIG_CPU_* */
+
+#endif /* __MIPS_PMU_H__ */
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index d0d24e0..9e61ecd 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -12,27 +12,11 @@
 #include <linux/init.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
+#include <asm/pmu.h>
 
 #include <loongson.h>			/* LOONGSON2_PERFCNT_IRQ */
 #include "op_impl.h"
 
-#define LOONGSON2_CPU_TYPE	"mips/loongson2"
-
-#define LOONGSON2_PERFCNT_OVERFLOW		(1ULL   << 31)
-
-#define LOONGSON2_PERFCTRL_EXL			(1UL	<<  0)
-#define LOONGSON2_PERFCTRL_KERNEL		(1UL    <<  1)
-#define LOONGSON2_PERFCTRL_SUPERVISOR		(1UL    <<  2)
-#define LOONGSON2_PERFCTRL_USER			(1UL    <<  3)
-#define LOONGSON2_PERFCTRL_ENABLE		(1UL    <<  4)
-#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
-	(((event) & 0x0f) << ((idx) ? 9 : 5))
-
-#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
-#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
-#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
-#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
-
 static struct loongson2_register_config {
 	unsigned int ctrl;
 	unsigned long long reset_counter1;
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..96f14e8 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -11,116 +11,10 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <asm/irq_regs.h>
+#include <asm/pmu.h>
 
 #include "op_impl.h"
 
-#define M_PERFCTL_EXL			(1UL      <<  0)
-#define M_PERFCTL_KERNEL		(1UL      <<  1)
-#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)
-#define M_PERFCTL_USER			(1UL      <<  3)
-#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)
-#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
-#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
-#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
-#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
-#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
-#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
-#define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
-#define M_PERFCTL_WIDE			(1UL      << 30)
-#define M_PERFCTL_MORE			(1UL      << 31)
-
-#define M_COUNTER_OVERFLOW		(1UL      << 31)
-
-static int (*save_perf_irq)(void);
-
-#ifdef CONFIG_MIPS_MT_SMP
-static int cpu_has_mipsmt_pertccounters;
-#define WHAT		(M_TC_EN_VPE | \
-			 M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
-#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
-			0 : cpu_data[smp_processor_id()].vpe_id)
-
-/*
- * The number of bits to shift to convert between counters per core and
- * counters per VPE.  There is no reasonable interface atm to obtain the
- * number of VPEs used by Linux and in the 34K this number is fixed to two
- * anyways so we hardcore a few things here for the moment.  The way it's
- * done here will ensure that oprofile VSMP kernel will run right on a lesser
- * core like a 24K also or with maxcpus=1.
- */
-static inline unsigned int vpe_shift(void)
-{
-	if (num_possible_cpus() > 1)
-		return 1;
-
-	return 0;
-}
-
-#else
-
-#define WHAT		0
-#define vpe_id()	0
-
-static inline unsigned int vpe_shift(void)
-{
-	return 0;
-}
-
-#endif
-
-static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
-{
-	return counters >> vpe_shift();
-}
-
-static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
-{
-	return counters << vpe_shift();
-}
-
-#define __define_perf_accessors(r, n, np)				\
-									\
-static inline unsigned int r_c0_ ## r ## n(void)			\
-{									\
-	unsigned int cpu = vpe_id();					\
-									\
-	switch (cpu) {							\
-	case 0:								\
-		return read_c0_ ## r ## n();				\
-	case 1:								\
-		return read_c0_ ## r ## np();				\
-	default:							\
-		BUG();							\
-	}								\
-	return 0;							\
-}									\
-									\
-static inline void w_c0_ ## r ## n(unsigned int value)			\
-{									\
-	unsigned int cpu = vpe_id();					\
-									\
-	switch (cpu) {							\
-	case 0:								\
-		write_c0_ ## r ## n(value);				\
-		return;							\
-	case 1:								\
-		write_c0_ ## r ## np(value);				\
-		return;							\
-	default:							\
-		BUG();							\
-	}								\
-	return;								\
-}									\
-
-__define_perf_accessors(perfcntr, 0, 2)
-__define_perf_accessors(perfcntr, 1, 3)
-__define_perf_accessors(perfcntr, 2, 0)
-__define_perf_accessors(perfcntr, 3, 1)
-
-__define_perf_accessors(perfctrl, 0, 2)
-__define_perf_accessors(perfctrl, 1, 3)
-__define_perf_accessors(perfctrl, 2, 0)
-__define_perf_accessors(perfctrl, 3, 1)
 
 struct op_mips_model op_model_mipsxx_ops;
 
@@ -242,61 +136,7 @@ static int mipsxx_perfcount_handler(void)
 	return handled;
 }
 
-#define M_CONFIG1_PC	(1 << 4)
-
-static inline int __n_counters(void)
-{
-	if (!(read_c0_config1() & M_CONFIG1_PC))
-		return 0;
-	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
-		return 1;
-	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
-		return 2;
-	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
-		return 3;
-
-	return 4;
-}
-
-static inline int n_counters(void)
-{
-	int counters;
-
-	switch (current_cpu_type()) {
-	case CPU_R10000:
-		counters = 2;
-		break;
-
-	case CPU_R12000:
-	case CPU_R14000:
-		counters = 4;
-		break;
-
-	default:
-		counters = __n_counters();
-	}
-
-	return counters;
-}
-
-static void reset_counters(void *arg)
-{
-	int counters = (int)(long)arg;
-	switch (counters) {
-	case 4:
-		w_c0_perfctrl3(0);
-		w_c0_perfcntr3(0);
-	case 3:
-		w_c0_perfctrl2(0);
-		w_c0_perfcntr2(0);
-	case 2:
-		w_c0_perfctrl1(0);
-		w_c0_perfcntr1(0);
-	case 1:
-		w_c0_perfctrl0(0);
-		w_c0_perfcntr0(0);
-	}
-}
+static int (*save_perf_irq)(void);
 
 static int __init mipsxx_init(void)
 {
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index 3aa8138..48e7487 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -9,24 +9,10 @@
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
+#include <asm/pmu.h>
 
 #include "op_impl.h"
 
-#define RM9K_COUNTER1_EVENT(event)	((event) << 0)
-#define RM9K_COUNTER1_SUPERVISOR	(1ULL    <<  7)
-#define RM9K_COUNTER1_KERNEL		(1ULL    <<  8)
-#define RM9K_COUNTER1_USER		(1ULL    <<  9)
-#define RM9K_COUNTER1_ENABLE		(1ULL    << 10)
-#define RM9K_COUNTER1_OVERFLOW		(1ULL    << 15)
-
-#define RM9K_COUNTER2_EVENT(event)	((event) << 16)
-#define RM9K_COUNTER2_SUPERVISOR	(1ULL    << 23)
-#define RM9K_COUNTER2_KERNEL		(1ULL    << 24)
-#define RM9K_COUNTER2_USER		(1ULL    << 25)
-#define RM9K_COUNTER2_ENABLE		(1ULL    << 26)
-#define RM9K_COUNTER2_OVERFLOW		(1ULL    << 31)
-
-extern unsigned int rm9000_perfcount_irq;
 
 static struct rm9k_register_config {
 	unsigned int control;
-- 
1.6.3.3

[PATCH v5 02/12] MIPS: use generic atomic64 in non-64bit kernels

[Deng-Cheng Zhu]

64bit kernel has already had its atomic64 functions. Except for that, we
use the generic spinlocked version. The atomic64 types and related
functions are needed for the Linux performance counter subsystem.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/Kconfig              |    1 +
 arch/mips/include/asm/atomic.h |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cdaae94..ef3d8ca 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,6 +4,7 @@ config MIPS
 	select HAVE_GENERIC_DMA_COHERENT
 	select HAVE_IDE
 	select HAVE_OPROFILE
+	select GENERIC_ATOMIC64 if !64BIT
 	select HAVE_ARCH_KGDB
 	select HAVE_FUNCTION_TRACER
 	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 59dc0c7..23990cb 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -782,6 +782,10 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
  */
 #define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
 
+#else /* ! CONFIG_64BIT */
+
+#include <asm-generic/atomic64.h>
+
 #endif /* CONFIG_64BIT */
 
 /*
-- 
1.6.3.3

[PATCH v5 03/12] MIPS: add support for software performance events

[Deng-Cheng Zhu]

Software events are required as part of the measurable stuff by the
Linux performance counter subsystem. Here is the list of events added by
this patch:
PERF_COUNT_SW_PAGE_FAULTS
PERF_COUNT_SW_PAGE_FAULTS_MIN
PERF_COUNT_SW_PAGE_FAULTS_MAJ
PERF_COUNT_SW_ALIGNMENT_FAULTS
PERF_COUNT_SW_EMULATION_FAULTS

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/Kconfig            |    2 ++
 arch/mips/kernel/traps.c     |   18 +++++++++++++++---
 arch/mips/kernel/unaligned.c |    5 +++++
 arch/mips/math-emu/cp1emu.c  |    3 +++
 arch/mips/mm/fault.c         |   11 +++++++++--
 5 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ef3d8ca..1bccfe5 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,6 +4,8 @@ config MIPS
 	select HAVE_GENERIC_DMA_COHERENT
 	select HAVE_IDE
 	select HAVE_OPROFILE
+	select HAVE_PERF_EVENTS
+	select PERF_USE_VMALLOC
 	select GENERIC_ATOMIC64 if !64BIT
 	select HAVE_ARCH_KGDB
 	select HAVE_FUNCTION_TRACER
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 8bdd6a6..d16b3fc 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -27,6 +27,7 @@
 #include <linux/kdebug.h>
 #include <linux/notifier.h>
 #include <linux/kdb.h>
+#include <linux/perf_event.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
@@ -570,10 +571,16 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
  */
 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 {
-	if ((opcode & OPCODE) == LL)
+	if ((opcode & OPCODE) == LL) {
+		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+				1, 0, regs, 0);
 		return simulate_ll(regs, opcode);
-	if ((opcode & OPCODE) == SC)
+	}
+	if ((opcode & OPCODE) == SC) {
+		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+				1, 0, regs, 0);
 		return simulate_sc(regs, opcode);
+	}
 
 	return -1;			/* Must be something else ... */
 }
@@ -589,6 +596,8 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 		int rd = (opcode & RD) >> 11;
 		int rt = (opcode & RT) >> 16;
+		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+				1, 0, regs, 0);
 		switch (rd) {
 		case 0:		/* CPU number */
 			regs->regs[rt] = smp_processor_id();
@@ -624,8 +633,11 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 
 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 {
-	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
+	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+				1, 0, regs, 0);
 		return 0;
+	}
 
 	return -1;			/* Must be something else ... */
 }
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 69b039c..a319c7a 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -78,6 +78,7 @@
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
 #include <asm/asm.h>
 #include <asm/branch.h>
 #include <asm/byteorder.h>
@@ -109,6 +110,8 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 	unsigned long value;
 	unsigned int res;
 
+	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+			1, 0, regs, 0);
 	regs->regs[0] = 0;
 
 	/*
@@ -513,6 +516,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
 	unsigned int __user *pc;
 	mm_segment_t seg;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
+			1, 0, regs, regs->cp0_badvaddr);
 	/*
 	 * Did we catch a fault trying to load an instruction?
 	 * Or are we running in MIPS16 mode?
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 47842b7..fd180ea 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -37,6 +37,7 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
 
 #include <asm/inst.h>
 #include <asm/bootinfo.h>
@@ -259,6 +260,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
 	}
 
       emul:
+	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+			1, 0, xcp, 0);
 	MIPS_FPU_EMU_INC_STATS(emulated);
 	switch (MIPSInst_OPCODE(ir)) {
 	case ldc1_op:{
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index b78f7d9..5987d2b 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -18,6 +18,7 @@
 #include <linux/smp.h>
 #include <linux/vt_kern.h>		/* For unblank_screen() */
 #include <linux/module.h>
+#include <linux/perf_event.h>
 
 #include <asm/branch.h>
 #include <asm/mmu_context.h>
@@ -132,6 +133,7 @@ good_area:
 	 * the fault.
 	 */
 	fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+	perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
@@ -139,10 +141,15 @@ good_area:
 			goto do_sigbus;
 		BUG();
 	}
-	if (fault & VM_FAULT_MAJOR)
+	if (fault & VM_FAULT_MAJOR) {
+		perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
+				1, 0, regs, address);
 		tsk->maj_flt++;
-	else
+	} else {
+		perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+				1, 0, regs, address);
 		tsk->min_flt++;
+	}
 
 	up_read(&mm->mmap_sem);
 	return;
-- 
1.6.3.3

[PATCH v5 04/12] MIPS: add support for hardware performance events (skeleton)

[Deng-Cheng Zhu]

This patch provides the skeleton of the HW perf event support. To enable
this feature, we can not choose the SMTC kernel; Oprofile should be
disabled; kernel performance events be selected. Then we can enable it in
Kernel type menu.

Oprofile for MIPS platforms initializes irq at arch init time. Currently
we do not change this logic to allow PMU reservation.

If a platform has EIC, we can use the irq base and perf counter irq
offset defines for the interrupt controller in mipspmu_get_irq().

Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely,
mipsxx/loongson2/rm9000, can be supported by adding corresponding lower
level C files at the bottom. The suggested names of these files are
perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for
example, we can do this by adding "#include perf_event_mipsxx.c" at the
bottom of perf_event.c.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/Kconfig                  |    8 +
 arch/mips/include/asm/perf_event.h |   28 ++
 arch/mips/kernel/Makefile          |    2 +
 arch/mips/kernel/perf_event.c      |  503 ++++++++++++++++++++++++++++++++++++
 4 files changed, 541 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/perf_event.h
 create mode 100644 arch/mips/kernel/perf_event.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1bccfe5..27577b4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1888,6 +1888,14 @@ config NODES_SHIFT
 	default "6"
 	depends on NEED_MULTIPLE_NODES
 
+config HW_PERF_EVENTS
+	bool "Enable hardware performance counter support for perf events"
+	depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
+	default y
+	help
+	  Enable hardware performance counter support for perf events. If
+	  disabled, perf events will use software events only.
+
 source "mm/Kconfig"
 
 config SMP
diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h
new file mode 100644
index 0000000..bcf54bc
--- /dev/null
+++ b/arch/mips/include/asm/perf_event.h
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/mips/include/asm/perf_event.h
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __MIPS_PERF_EVENT_H__
+#define __MIPS_PERF_EVENT_H__
+
+extern int (*perf_irq)(void);
+
+/*
+ * MIPS performance counters do not raise NMI upon overflow, a regular
+ * interrupt will be signaled. Hence we can do the pending perf event
+ * work at the tail of the irq handler.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+#endif /* __MIPS_PERF_EVENT_H__ */
+
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 7a6ac50..c934ab7 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -101,6 +101,8 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
 obj-$(CONFIG_MIPS_CPUFREQ)	+= cpufreq/
 
+obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
+
 EXTRA_CFLAGS += -Werror
 
 CPPFLAGS_vmlinux.lds		:= $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
new file mode 100644
index 0000000..788815f
--- /dev/null
+++ b/arch/mips/kernel/perf_event.c
@@ -0,0 +1,503 @@
+/*
+ * Linux performance counter support for MIPS.
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu
+ *
+ * This code is based on the implementation for ARM, which is in turn
+ * based on the sparc64 perf event code and the x86 code. Performance
+ * counter access is based on the MIPS Oprofile code.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/uaccess.h>
+
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/stacktrace.h>
+#include <asm/pmu.h>
+
+
+#define MAX_PERIOD ((1ULL << 32) - 1)
+
+struct cpu_hw_events {
+	/* Array of events on this cpu. */
+	struct perf_event	*events[MIPS_MAX_HWEVENTS];
+
+	/*
+	 * Set the bit (indexed by the counter number) when the counter
+	 * is used for an event.
+	 */
+	unsigned long		used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+	/*
+	 * The borrowed MSB for the performance counter. A MIPS performance
+	 * counter uses its bit 31 as a factor of determining whether a counter
+	 * overflow should be signaled. So here we use a separate MSB for each
+	 * counter to make things easy.
+	 */
+	unsigned long		msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+	/*
+	 * Software copy of the control register for each performance counter.
+	 * MIPS CPUs vary in performance counters. They use this differently,
+	 * and even may not use it.
+	 */
+	unsigned int		saved_ctrl[MIPS_MAX_HWEVENTS];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
+	.saved_ctrl = {0},
+};
+
+/* The description of MIPS performance events. */
+struct mips_perf_event {
+	unsigned int event_id;
+	/*
+	 * MIPS performance counters are indexed starting from 0.
+	 * CNTR_EVEN indicates the indexes of the counters to be used are
+	 * even numbers.
+	 */
+	unsigned int cntr_mask;
+	#define CNTR_EVEN	0x55555555
+	#define CNTR_ODD	0xaaaaaaaa
+#ifdef CONFIG_MIPS_MT_SMP
+	enum {
+		T  = 0,
+		V  = 1,
+		P  = 2,
+	} range;
+#else
+	#define T
+	#define V
+	#define P
+#endif
+};
+
+#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+struct mips_pmu {
+	const char	*name;
+	irqreturn_t	(*handle_irq)(int irq, void *dev);
+	int		(*handle_shared_irq)(void);
+	void		(*start)(void);
+	void		(*stop)(void);
+	int		(*alloc_counter)(struct cpu_hw_events *cpuc,
+					struct hw_perf_event *hwc);
+	unsigned int	(*read_counter)(unsigned int idx);
+	void		(*write_counter)(unsigned int idx, unsigned int val);
+	void		(*enable_event)(struct hw_perf_event *evt, int idx);
+	void		(*disable_event)(int idx);
+	const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
+	const struct mips_perf_event (*cache_event_map)
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX];
+	unsigned int	num_counters;
+};
+
+static const struct mips_pmu *mipspmu;
+
+static int
+mipspmu_event_set_period(struct perf_event *event,
+			struct hw_perf_event *hwc,
+			int idx)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	s64 left = atomic64_read(&hwc->period_left);
+	s64 period = hwc->sample_period;
+	int ret = 0;
+	unsigned long flags, uleft;
+
+	if (unlikely(left <= -period)) {
+		left = period;
+		atomic64_set(&hwc->period_left, left);
+		hwc->last_period = period;
+		ret = 1;
+	}
+
+	if (unlikely(left <= 0)) {
+		left += period;
+		atomic64_set(&hwc->period_left, left);
+		hwc->last_period = period;
+		ret = 1;
+	}
+
+	if (left > (s64)MAX_PERIOD)
+		left = MAX_PERIOD;
+
+	atomic64_set(&hwc->prev_count, (u64)-left);
+
+	local_irq_save(flags);
+	uleft = (u64)(-left) & 0xffffffff;
+	test_bit(31, &uleft) ?
+		set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
+	mipspmu->write_counter(idx, (u64)(-left) & 0x7fffffff);
+	local_irq_restore(flags);
+
+	perf_event_update_userpage(event);
+
+	return ret;
+}
+
+static int mipspmu_enable(struct perf_event *event)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	struct hw_perf_event *hwc = &event->hw;
+	int idx;
+	int err = 0;
+
+	/* To look for a free counter for this event. */
+	idx = mipspmu->alloc_counter(cpuc, hwc);
+	if (idx < 0) {
+		err = idx;
+		goto out;
+	}
+
+	/*
+	 * If there is an event in the counter we are going to use then
+	 * make sure it is disabled.
+	 */
+	event->hw.idx = idx;
+	mipspmu->disable_event(idx);
+	cpuc->events[idx] = event;
+
+	/* Set the period for the event. */
+	mipspmu_event_set_period(event, hwc, idx);
+
+	/* Enable the event. */
+	mipspmu->enable_event(hwc, idx);
+
+	/* Propagate our changes to the userspace mapping. */
+	perf_event_update_userpage(event);
+
+out:
+	return err;
+}
+
+static void mipspmu_event_update(struct perf_event *event,
+			struct hw_perf_event *hwc,
+			int idx)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	unsigned long flags;
+	int shift = 64 - 32;
+	s64 prev_raw_count, new_raw_count;
+	s64 delta;
+
+again:
+	prev_raw_count = atomic64_read(&hwc->prev_count);
+	local_irq_save(flags);
+	/* Make the counter value be a "real" one. */
+	new_raw_count = mipspmu->read_counter(idx);
+	if (new_raw_count & (test_bit(idx, cpuc->msbs) << 31)) {
+		new_raw_count &= 0x7fffffff;
+		clear_bit(idx, cpuc->msbs);
+	} else
+		new_raw_count |= (test_bit(idx, cpuc->msbs) << 31);
+	local_irq_restore(flags);
+
+	if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+				new_raw_count) != prev_raw_count)
+		goto again;
+
+	delta = (new_raw_count << shift) - (prev_raw_count << shift);
+	delta >>= shift;
+
+	atomic64_add(delta, &event->count);
+	atomic64_sub(delta, &hwc->period_left);
+
+	return;
+}
+
+static void mipspmu_disable(struct perf_event *event)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	struct hw_perf_event *hwc = &event->hw;
+	int idx = hwc->idx;
+
+
+	WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+	/* We are working on a local event. */
+	mipspmu->disable_event(idx);
+
+	barrier();
+
+	mipspmu_event_update(event, hwc, idx);
+	cpuc->events[idx] = NULL;
+	clear_bit(idx, cpuc->used_mask);
+
+	perf_event_update_userpage(event);
+}
+
+static void mipspmu_unthrottle(struct perf_event *event)
+{
+	struct hw_perf_event *hwc = &event->hw;
+
+	mipspmu->enable_event(hwc, hwc->idx);
+}
+
+static void mipspmu_read(struct perf_event *event)
+{
+	struct hw_perf_event *hwc = &event->hw;
+
+	/* Don't read disabled counters! */
+	if (hwc->idx < 0)
+		return;
+
+	mipspmu_event_update(event, hwc, hwc->idx);
+}
+
+static struct pmu pmu = {
+	.enable		= mipspmu_enable,
+	.disable	= mipspmu_disable,
+	.unthrottle	= mipspmu_unthrottle,
+	.read		= mipspmu_read,
+};
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+static int mips_pmu_irq = -1;
+static int (*save_perf_irq)(void);
+
+static int mipspmu_get_irq(void)
+{
+	int err;
+
+	if (cpu_has_veic) {
+		/*
+		 * Using platform specific interrupt controller defines.
+		 */
+#ifdef MSC01E_INT_BASE
+		mips_pmu_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+#endif
+	} else if (cp0_perfcount_irq >= 0) {
+		/*
+		 * Some CPUs have explicitly defined their perfcount irq.
+		 */
+#if defined(CONFIG_CPU_RM9000)
+		mips_pmu_irq = rm9000_perfcount_irq;
+#elif defined(CONFIG_CPU_LOONGSON2)
+		mips_pmu_irq = LOONGSON2_PERFCNT_IRQ;
+#else
+		mips_pmu_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+#endif
+	}
+
+	if (mips_pmu_irq >= 0) {
+		/* Request my own irq handler. */
+		err = request_irq(mips_pmu_irq, mipspmu->handle_irq,
+			IRQF_DISABLED | IRQF_NOBALANCING,
+			"mips_perf_pmu", NULL);
+		if (err) {
+			pr_warning("Unable to request IRQ%d for MIPS "
+			   "performance counters!\n", mips_pmu_irq);
+		}
+	} else if (cp0_perfcount_irq < 0) {
+		/*
+		 * We are sharing the irq number with the timer interrupt.
+		 */
+		save_perf_irq = perf_irq;
+		perf_irq = mipspmu->handle_shared_irq;
+		err = 0;
+	} else {
+		pr_warning("The platform hasn't properly defined its "
+			"interrupt controller.\n");
+		err = -ENOENT;
+	}
+
+	return err;
+}
+
+static void mipspmu_free_irq(void)
+{
+	if (mips_pmu_irq >= 0)
+		free_irq(mips_pmu_irq, NULL);
+	else if (cp0_perfcount_irq < 0)
+		perf_irq = save_perf_irq;
+
+	mips_pmu_irq = -1;
+}
+
+static inline unsigned int
+mipspmu_perf_event_encode(const struct mips_perf_event *pev)
+{
+/*
+ * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
+ * event_id.
+ */
+#ifdef CONFIG_MIPS_MT_SMP
+	return ((unsigned int)pev->range << 24) |
+		(pev->cntr_mask & 0xffff00) |
+		(pev->event_id & 0xff);
+#else
+	return (pev->cntr_mask & 0xffff00) |
+		(pev->event_id & 0xff);
+#endif
+}
+
+static const struct mips_perf_event *
+mipspmu_map_general_event(int idx)
+{
+	const struct mips_perf_event *pev;
+
+	pev = ((*mipspmu->general_event_map)[idx].event_id ==
+		UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
+		&(*mipspmu->general_event_map)[idx]);
+
+	return pev;
+}
+
+static const struct mips_perf_event *
+mipspmu_map_cache_event(u64 config)
+{
+	unsigned int cache_type, cache_op, cache_result;
+	const struct mips_perf_event *pev;
+
+	cache_type = (config >> 0) & 0xff;
+	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+		return ERR_PTR(-EINVAL);
+
+	cache_op = (config >> 8) & 0xff;
+	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+		return ERR_PTR(-EINVAL);
+
+	cache_result = (config >> 16) & 0xff;
+	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+		return ERR_PTR(-EINVAL);
+
+	pev = &((*mipspmu->cache_event_map)
+					[cache_type]
+					[cache_op]
+					[cache_result]);
+
+	if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
+		return ERR_PTR(-EOPNOTSUPP);
+
+	return pev;
+
+}
+
+static int validate_event(struct cpu_hw_events *cpuc,
+	       struct perf_event *event)
+{
+	struct hw_perf_event fake_hwc = event->hw;
+
+	if (event->pmu && event->pmu != &pmu)
+		return 0;
+
+	return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
+}
+
+static int validate_group(struct perf_event *event)
+{
+	struct perf_event *sibling, *leader = event->group_leader;
+	struct cpu_hw_events fake_cpuc;
+
+	memset(&fake_cpuc, 0, sizeof(fake_cpuc));
+
+	if (!validate_event(&fake_cpuc, leader))
+		return -ENOSPC;
+
+	list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+		if (!validate_event(&fake_cpuc, sibling))
+			return -ENOSPC;
+	}
+
+	if (!validate_event(&fake_cpuc, event))
+		return -ENOSPC;
+
+	return 0;
+}
+
+/*
+ * mipsxx/rm9000/loongson2 have different performance counters, they have
+ * specific low-level init routines.
+ */
+static int __hw_perf_event_init(struct perf_event *event);
+
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+	if (atomic_dec_and_mutex_lock(&active_events,
+				&pmu_reserve_mutex)) {
+		/*
+		 * We must not call the destroy function with interrupts
+		 * disabled.
+		 */
+		on_each_cpu(reset_counters,
+			(void *)(long)mipspmu->num_counters, 1);
+		mipspmu_free_irq();
+		mutex_unlock(&pmu_reserve_mutex);
+	}
+}
+
+const struct pmu *hw_perf_event_init(struct perf_event *event)
+{
+	int err = 0;
+
+	if (!mipspmu || event->cpu >= nr_cpumask_bits ||
+		(event->cpu >= 0 && !cpu_online(event->cpu)))
+		return ERR_PTR(-ENODEV);
+
+	if (!atomic_inc_not_zero(&active_events)) {
+		if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
+			atomic_dec(&active_events);
+			return ERR_PTR(-ENOSPC);
+		}
+
+		mutex_lock(&pmu_reserve_mutex);
+		if (atomic_read(&active_events) == 0)
+			err = mipspmu_get_irq();
+
+		if (!err)
+			atomic_inc(&active_events);
+		mutex_unlock(&pmu_reserve_mutex);
+	}
+
+	if (err)
+		return ERR_PTR(err);
+
+	err = __hw_perf_event_init(event);
+	if (err)
+		hw_perf_event_destroy(event);
+
+	return err ? ERR_PTR(err) : &pmu;
+}
+
+void hw_perf_enable(void)
+{
+	if (mipspmu)
+		mipspmu->start();
+}
+
+void hw_perf_disable(void)
+{
+	if (mipspmu)
+		mipspmu->stop();
+}
+
+/* This is needed by specific irq handlers in perf_event_*.c */
+static void
+handle_associated_event(struct cpu_hw_events *cpuc,
+	int idx, struct perf_sample_data *data, struct pt_regs *regs)
+{
+	struct perf_event *event = cpuc->events[idx];
+	struct hw_perf_event *hwc = &event->hw;
+
+	mipspmu_event_update(event, hwc, idx);
+	data->period = event->hw.last_period;
+	if (!mipspmu_event_set_period(event, hwc, idx))
+		return;
+
+	if (perf_event_overflow(event, 0, data, regs))
+		mipspmu->disable_event(idx);
+}
+
-- 
1.6.3.3

[PATCH v5 05/12] MIPS/Perf-events: add callchain support

[Deng-Cheng Zhu]

This patch adds callchain support for MIPS Perf-events. For more info on
this feature, please refer to tools/perf/Documentation/perf-report.txt
and tools/perf/design.txt.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/kernel/perf_event.c |   98 ++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 97 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 788815f..63ea0e9 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -5,7 +5,8 @@
  *
  * This code is based on the implementation for ARM, which is in turn
  * based on the sparc64 perf event code and the x86 code. Performance
- * counter access is based on the MIPS Oprofile code.
+ * counter access is based on the MIPS Oprofile code. And the callchain
+ * support references the code of MIPS traps.c.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -501,3 +502,98 @@ handle_associated_event(struct cpu_hw_events *cpuc,
 		mipspmu->disable_event(idx);
 }
 
+/*
+ * Callchain handling code.
+ */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+		u64 ip)
+{
+	if (entry->nr < PERF_MAX_STACK_DEPTH)
+		entry->ip[entry->nr++] = ip;
+}
+
+static void
+perf_callchain_user(struct pt_regs *regs,
+		    struct perf_callchain_entry *entry)
+{
+	unsigned long *sp;
+	unsigned long addr;
+
+	callchain_store(entry, PERF_CONTEXT_USER);
+
+	if (!user_mode(regs))
+		regs = task_pt_regs(current);
+
+	sp = (unsigned long *)(regs->regs[29] & ~3);
+
+	while (!kstack_end(sp)) {
+		unsigned long __user *p =
+			(unsigned long __user *)(unsigned long)sp++;
+		if (__get_user(addr, p)) {
+			pr_warning("Performance counter callchain "
+				"suppport: Bad stack address.\n");
+			break;
+		}
+		callchain_store(entry, addr);
+	}
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+		      struct perf_callchain_entry *entry)
+{
+	unsigned long sp = regs->regs[29];
+	unsigned long ra = regs->regs[31];
+	unsigned long pc = regs->cp0_epc;
+
+	if (unlikely(!__kernel_text_address(pc))) {
+		pr_warning("Performance counter callchain support "
+			"error.\n");
+		return;
+	}
+
+	callchain_store(entry, PERF_CONTEXT_KERNEL);
+
+	do {
+		callchain_store(entry, pc);
+		pc = unwind_stack(current, &sp, pc, &ra);
+	} while (pc);
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+		  struct perf_callchain_entry *entry)
+{
+	int is_user;
+
+	if (!regs)
+		return;
+
+	is_user = user_mode(regs);
+
+	if (!current || !current->pid)
+		return;
+
+	if (is_user && current->state != TASK_RUNNING)
+		return;
+
+	if (!is_user)
+		perf_callchain_kernel(regs, entry);
+
+	if (current->mm)
+		perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+	struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+	entry->nr = 0;
+	perf_do_callchain(regs, entry);
+	return entry;
+}
+
-- 
1.6.3.3

[PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx)

[Deng-Cheng Zhu]

This patch adds the mipsxx Perf-event support based on the skeleton.
Generic hardware events and cache events are now fully implemented for
the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as
R10000/SB1), the generic hardware event tables and cache event tables
need to be filled out. To support other CPUs which have different PMU
than mipsxx, such as RM9000 and LOONGSON2, the additional files
perf_event_$cpu.c need to be created.

To test the functionality of Perf-event, you may want to compile the tool
"perf" for your MIPS platform. You can refer to the following URL:
http://www.linux-mips.org/archives/linux-mips/2010-04/msg00158.html

Please note: Before that patch is accepted, you can choose a "specific"
rmb() which is suitable for your platform -- an example is provided in
the description of that patch.

You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile
for your libs, includes, etc.

In case you encounter the boot failure in SMVP kernel on multi-threading
CPUs, you may take a look at:
http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/kernel/perf_event.c        |    2 +
 arch/mips/kernel/perf_event_mipsxx.c |  719 ++++++++++++++++++++++++++++++++++
 2 files changed, 721 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/kernel/perf_event_mipsxx.c

diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 63ea0e9..4c9b741 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -502,6 +502,8 @@ handle_associated_event(struct cpu_hw_events *cpuc,
 		mipspmu->disable_event(idx);
 }
 
+#include "perf_event_mipsxx.c"
+
 /*
  * Callchain handling code.
  */
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
new file mode 100644
index 0000000..87103bf
--- /dev/null
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -0,0 +1,719 @@
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
+    defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
+
+#define M_PERFCTL_COUNT_EVENT_WHENEVER		\
+	(M_PERFCTL_EXL | M_PERFCTL_KERNEL |	\
+	M_PERFCTL_USER | M_PERFCTL_SUPERVISOR |	\
+	M_PERFCTL_INTERRUPT_ENABLE)
+
+#ifdef CONFIG_MIPS_MT_SMP
+#define M_PERFCTL_CONFIG_MASK 0x3fff801f
+#else
+#define M_PERFCTL_CONFIG_MASK 0x1f
+#endif
+#define M_PERFCTL_EVENT_MASK 0xfe0
+
+static inline unsigned int
+mipsxx_pmu_read_counter(unsigned int idx)
+{
+	switch (idx) {
+	case 0:
+		return r_c0_perfcntr0();
+	case 1:
+		return r_c0_perfcntr1();
+	case 2:
+		return r_c0_perfcntr2();
+	case 3:
+		return r_c0_perfcntr3();
+	default:
+		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+		return 0;
+	}
+}
+
+static inline void
+mipsxx_pmu_write_counter(unsigned int idx, unsigned int val)
+{
+	switch (idx) {
+	case 0:
+		w_c0_perfcntr0(val);
+		return;
+	case 1:
+		w_c0_perfcntr1(val);
+		return;
+	case 2:
+		w_c0_perfcntr2(val);
+		return;
+	case 3:
+		w_c0_perfcntr3(val);
+		return;
+	}
+}
+
+static inline unsigned int
+mipsxx_pmu_read_control(unsigned int idx)
+{
+	switch (idx) {
+	case 0:
+		return r_c0_perfctrl0();
+	case 1:
+		return r_c0_perfctrl1();
+	case 2:
+		return r_c0_perfctrl2();
+	case 3:
+		return r_c0_perfctrl3();
+	default:
+		WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+		return 0;
+	}
+}
+
+static inline void
+mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
+{
+	switch (idx) {
+	case 0:
+		w_c0_perfctrl0(val);
+		return;
+	case 1:
+		w_c0_perfctrl1(val);
+		return;
+	case 2:
+		w_c0_perfctrl2(val);
+		return;
+	case 3:
+		w_c0_perfctrl3(val);
+		return;
+	}
+}
+
+#ifdef CONFIG_MIPS_MT_SMP
+static DEFINE_RWLOCK(pmuint_rwlock);
+#endif
+
+/* 24K/34K/1004K cores can share the same event map. */
+static const struct mips_perf_event mipsxxcore_event_map
+				[PERF_COUNT_HW_MAX] = {
+	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+	[PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+	[PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
+	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
+	[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 74K core has different branch event code. */
+static const struct mips_perf_event mipsxx74Kcore_event_map
+				[PERF_COUNT_HW_MAX] = {
+	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+	[PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+	[PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
+	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
+	[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 24K/34K/1004K cores can share the same cache event map. */
+static const struct mips_perf_event mipsxxcore_cache_map
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+	/*
+	 * Like some other architectures (e.g. ARM), the performance
+	 * counters don't differentiate between read and write
+	 * accesses/misses, so this isn't strictly correct, but it's the
+	 * best we can do. Writes and reads get combined.
+	 */
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(L1I)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
+		/*
+		 * Note that MIPS has only "hit" events countable for
+		 * the prefetch operation.
+		 */
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(LL)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
+		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
+		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(DTLB)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(ITLB)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(BPU)] = {
+	/* Using the same code for *HW_BRANCH* */
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+};
+
+/* 74K core has completely different cache event map. */
+static const struct mips_perf_event mipsxx74Kcore_cache_map
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+	/*
+	 * Like some other architectures (e.g. ARM), the performance
+	 * counters don't differentiate between read and write
+	 * accesses/misses, so this isn't strictly correct, but it's the
+	 * best we can do. Writes and reads get combined.
+	 */
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
+		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
+		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(L1I)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
+		/*
+		 * Note that MIPS has only "hit" events countable for
+		 * the prefetch operation.
+		 */
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(LL)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
+		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
+		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(DTLB)] = {
+	/* 74K core does not have specific DTLB events. */
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(ITLB)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+[C(BPU)] = {
+	/* Using the same code for *HW_BRANCH* */
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
+	},
+	[C(OP_PREFETCH)] = {
+		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+	},
+},
+};
+
+#ifdef CONFIG_MIPS_MT_SMP
+static void
+check_and_calc_range(struct perf_event *event,
+			const struct mips_perf_event *pev)
+{
+	struct hw_perf_event *hwc = &event->hw;
+
+	if (event->cpu >= 0) {
+		if (pev->range > V) {
+			/*
+			 * The user selected an event that is processor
+			 * wide, while expecting it to be VPE wide.
+			 */
+			hwc->config_base |= M_TC_EN_ALL;
+		} else {
+			/*
+			 * FIXME: cpu_data[event->cpu].vpe_id reports 0
+			 * for both CPUs.
+			 */
+			hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
+			hwc->config_base |= M_TC_EN_VPE;
+		}
+	} else
+		hwc->config_base |= M_TC_EN_ALL;
+}
+#else
+static void
+check_and_calc_range(struct perf_event *event,
+			const struct mips_perf_event *pev)
+{
+}
+#endif
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+	struct perf_event_attr *attr = &event->attr;
+	struct hw_perf_event *hwc = &event->hw;
+	const struct mips_perf_event *pev;
+	int err;
+
+	/* Returning MIPS event descriptor for generic perf event. */
+	if (PERF_TYPE_HARDWARE == event->attr.type) {
+		if (event->attr.config >= PERF_COUNT_HW_MAX)
+			return -EINVAL;
+		pev = mipspmu_map_general_event(event->attr.config);
+	} else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+		pev = mipspmu_map_cache_event(event->attr.config);
+	} else {
+		/* The event type is not (yet) supported. */
+		return -EOPNOTSUPP;
+	}
+
+	if (IS_ERR(pev))
+		return PTR_ERR(pev);
+
+	/*
+	 * We allow max flexibility on how each individual counter shared
+	 * by the single CPU operates (the mode exclusion and the range).
+	 */
+	hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
+
+	/* Calculate range bits and validate it. */
+	if (num_possible_cpus() > 1)
+		check_and_calc_range(event, pev);
+
+	hwc->event_base = mipspmu_perf_event_encode(pev);
+
+	if (!attr->exclude_user)
+		hwc->config_base |= M_PERFCTL_USER;
+	if (!attr->exclude_kernel) {
+		hwc->config_base |= M_PERFCTL_KERNEL;
+		/* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
+		hwc->config_base |= M_PERFCTL_EXL;
+	}
+	if (!attr->exclude_hv)
+		hwc->config_base |= M_PERFCTL_SUPERVISOR;
+
+	hwc->config_base &= M_PERFCTL_CONFIG_MASK;
+	/*
+	 * The event can belong to another cpu. We do not assign a local
+	 * counter for it for now.
+	 */
+	hwc->idx = -1;
+	hwc->config = 0;
+
+	if (!hwc->sample_period) {
+		hwc->sample_period  = MAX_PERIOD;
+		hwc->last_period    = hwc->sample_period;
+		atomic64_set(&hwc->period_left, hwc->sample_period);
+	}
+
+	err = 0;
+	if (event->group_leader != event) {
+		err = validate_group(event);
+		if (err)
+			return -EINVAL;
+	}
+
+	event->destroy = hw_perf_event_destroy;
+
+	return err;
+}
+
+static void pause_local_counters(void)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	int counters = mipspmu->num_counters;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	switch (counters) {
+	case 4:
+		cpuc->saved_ctrl[3] = r_c0_perfctrl3();
+		w_c0_perfctrl3(cpuc->saved_ctrl[3] &
+			~M_PERFCTL_COUNT_EVENT_WHENEVER);
+	case 3:
+		cpuc->saved_ctrl[2] = r_c0_perfctrl2();
+		w_c0_perfctrl2(cpuc->saved_ctrl[2] &
+			~M_PERFCTL_COUNT_EVENT_WHENEVER);
+	case 2:
+		cpuc->saved_ctrl[1] = r_c0_perfctrl1();
+		w_c0_perfctrl1(cpuc->saved_ctrl[1] &
+			~M_PERFCTL_COUNT_EVENT_WHENEVER);
+	case 1:
+		cpuc->saved_ctrl[0] = r_c0_perfctrl0();
+		w_c0_perfctrl0(cpuc->saved_ctrl[0] &
+			~M_PERFCTL_COUNT_EVENT_WHENEVER);
+	}
+	local_irq_restore(flags);
+}
+
+static void resume_local_counters(void)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	int counters = mipspmu->num_counters;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	switch (counters) {
+	case 4:
+		w_c0_perfctrl3(cpuc->saved_ctrl[3]);
+	case 3:
+		w_c0_perfctrl2(cpuc->saved_ctrl[2]);
+	case 2:
+		w_c0_perfctrl1(cpuc->saved_ctrl[1]);
+	case 1:
+		w_c0_perfctrl0(cpuc->saved_ctrl[0]);
+	}
+	local_irq_restore(flags);
+}
+
+static int mipsxx_pmu_handle_shared_irq(void)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	struct perf_sample_data data;
+	unsigned int counters = mipspmu->num_counters;
+	unsigned int counter;
+	int handled = IRQ_NONE;
+	struct pt_regs *regs;
+
+	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+		return handled;
+
+	/*
+	 * First we pause the local counters, so that when we are locked
+	 * here, the counters are all paused. When it gets locked due to
+	 * perf_disable(), the timer interrupt handler will be delayed.
+	 *
+	 * See also mipsxx_pmu_start().
+	 */
+	pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+	read_lock(&pmuint_rwlock);
+#endif
+
+	regs = get_irq_regs();
+
+	perf_sample_data_init(&data, 0);
+
+	switch (counters) {
+#define HANDLE_COUNTER(n)						\
+	case n + 1:							\
+		if (test_bit(n, cpuc->used_mask)) {			\
+			counter = r_c0_perfcntr ## n();			\
+			if (counter & M_COUNTER_OVERFLOW) {		\
+				w_c0_perfcntr ## n(counter &		\
+						0x7fffffff);		\
+				if (test_and_change_bit(n, cpuc->msbs))	\
+					handle_associated_event(cpuc,	\
+						n, &data, regs);	\
+				handled = IRQ_HANDLED;			\
+			}						\
+		}
+	HANDLE_COUNTER(3)
+	HANDLE_COUNTER(2)
+	HANDLE_COUNTER(1)
+	HANDLE_COUNTER(0)
+	}
+
+	/*
+	 * Do all the work for the pending perf events. We can do this
+	 * in here because the performance counter interrupt is a regular
+	 * interrupt, not NMI.
+	 */
+	if (handled == IRQ_HANDLED)
+		perf_event_do_pending();
+
+#ifdef CONFIG_MIPS_MT_SMP
+	read_unlock(&pmuint_rwlock);
+#endif
+	resume_local_counters();
+	return handled;
+}
+
+static irqreturn_t
+mipsxx_pmu_handle_irq(int irq, void *dev)
+{
+	return mipsxx_pmu_handle_shared_irq();
+}
+
+static void mipsxx_pmu_start(void)
+{
+#ifdef CONFIG_MIPS_MT_SMP
+	write_unlock(&pmuint_rwlock);
+#endif
+	resume_local_counters();
+}
+
+/*
+ * MIPS performance counters can be per-TC. The control registers can
+ * not be directly accessed accross CPUs. Hence if we want to do global
+ * control, we need cross CPU calls. on_each_cpu() can help us, but we
+ * can not make sure this function is called with interrupts enabled. So
+ * here we pause local counters and then grab a rwlock and leave the
+ * counters on other CPUs alone. If any counter interrupt raises while
+ * we own the write lock, simply pause local counters on that CPU and
+ * spin in the handler. Also we know we won't be switched to another
+ * CPU after pausing local counters and before grabbing the lock.
+ */
+static void mipsxx_pmu_stop(void)
+{
+	pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+	write_lock(&pmuint_rwlock);
+#endif
+}
+
+static int
+mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
+			struct hw_perf_event *hwc)
+{
+	int i;
+
+	/*
+	 * We only need to care the counter mask. The range has been
+	 * checked definitely.
+	 */
+	unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
+
+	for (i = mipspmu->num_counters - 1; i >= 0; i--) {
+		/*
+		 * Note that some MIPS perf events can be counted by both
+		 * even and odd counters, wheresas many other are only by
+		 * even _or_ odd counters. This introduces an issue that
+		 * when the former kind of event takes the counter the
+		 * latter kind of event wants to use, then the "counter
+		 * allocation" for the latter event will fail. In fact if
+		 * they can be dynamically swapped, they both feel happy.
+		 * But here we leave this issue alone for now.
+		 */
+		if (test_bit(i, &cntr_mask) &&
+			!test_and_set_bit(i, cpuc->used_mask))
+			return i;
+	}
+
+	return -EAGAIN;
+}
+
+static void
+mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	unsigned long flags;
+
+	WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+	local_irq_save(flags);
+	cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
+		(evt->config_base & M_PERFCTL_CONFIG_MASK) |
+		/* Make sure interrupt enabled. */
+		M_PERFCTL_INTERRUPT_ENABLE;
+	/*
+	 * We do not actually let the counter run. Leave it until start().
+	 */
+	local_irq_restore(flags);
+}
+
+static void
+mipsxx_pmu_disable_event(int idx)
+{
+	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+	unsigned long flags;
+
+	WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+	local_irq_save(flags);
+	cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
+		~M_PERFCTL_COUNT_EVENT_WHENEVER;
+	mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
+	local_irq_restore(flags);
+}
+
+static struct mips_pmu mipsxxcore_pmu = {
+	.handle_irq = mipsxx_pmu_handle_irq,
+	.handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+	.start = mipsxx_pmu_start,
+	.stop = mipsxx_pmu_stop,
+	.alloc_counter = mipsxx_pmu_alloc_counter,
+	.read_counter = mipsxx_pmu_read_counter,
+	.write_counter = mipsxx_pmu_write_counter,
+	.enable_event = mipsxx_pmu_enable_event,
+	.disable_event = mipsxx_pmu_disable_event,
+	.general_event_map = &mipsxxcore_event_map,
+	.cache_event_map = &mipsxxcore_cache_map,
+};
+
+static struct mips_pmu mipsxx74Kcore_pmu = {
+	.handle_irq = mipsxx_pmu_handle_irq,
+	.handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+	.start = mipsxx_pmu_start,
+	.stop = mipsxx_pmu_stop,
+	.alloc_counter = mipsxx_pmu_alloc_counter,
+	.read_counter = mipsxx_pmu_read_counter,
+	.write_counter = mipsxx_pmu_write_counter,
+	.enable_event = mipsxx_pmu_enable_event,
+	.disable_event = mipsxx_pmu_disable_event,
+	.general_event_map = &mipsxx74Kcore_event_map,
+	.cache_event_map = &mipsxx74Kcore_cache_map,
+};
+
+static int __init
+init_hw_perf_events(void)
+{
+	int counters;
+
+	pr_info("Performance counters: ");
+
+	counters = n_counters();
+	if (counters == 0) {
+		pr_cont("No available PMU.\n");
+		return -ENODEV;
+	}
+
+#ifdef CONFIG_MIPS_MT_SMP
+	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
+	if (!cpu_has_mipsmt_pertccounters)
+		counters = counters_total_to_per_cpu(counters);
+#endif
+
+	on_each_cpu(reset_counters, (void *)(long)counters, 1);
+
+	switch (current_cpu_type()) {
+	case CPU_24K:
+		mipsxxcore_pmu.name = "mips/24K";
+		mipsxxcore_pmu.num_counters = counters;
+		mipspmu = &mipsxxcore_pmu;
+		break;
+	case CPU_34K:
+		mipsxxcore_pmu.name = "mips/34K";
+		mipsxxcore_pmu.num_counters = counters;
+		mipspmu = &mipsxxcore_pmu;
+		break;
+	case CPU_74K:
+		mipsxx74Kcore_pmu.name = "mips/74K";
+		mipsxx74Kcore_pmu.num_counters = counters;
+		mipspmu = &mipsxx74Kcore_pmu;
+		break;
+	case CPU_1004K:
+		mipsxxcore_pmu.name = "mips/1004K";
+		mipsxxcore_pmu.num_counters = counters;
+		mipspmu = &mipsxxcore_pmu;
+		break;
+	default:
+		pr_cont("Either hardware does not support performance "
+			"counters, or not yet implemented.\n");
+		return -ENODEV;
+	}
+
+	if (mipspmu)
+		pr_cont("%s PMU enabled, %d counters available to each "
+			"CPU\n", mipspmu->name, mipspmu->num_counters);
+
+	return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+#endif /* defined(CONFIG_CPU_MIPS32)... */
-- 
1.6.3.3

[PATCH v5 07/12] MIPS/Perf-events: add raw event support for mipsxx 24K/34K/74K/1004K

[Deng-Cheng Zhu]

Raw event is an important part of Perf-events. It helps the user collect
performance data for events that are not listed as the generic hardware
events and cache events but ARE supported by the CPU's PMU.

This patch adds this feature for mipsxx 24K/34K/74K/1004K. For how to use
it, please refer to processor core software user's manual and the
comments for mipsxx_pmu_map_raw_event() for more details.

Please note that this is a "precise" implementation, which means the
kernel will check whether the requested raw events are supported by this
CPU and which hardware counters can be assigned for them.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/kernel/perf_event.c        |    4 +
 arch/mips/kernel/perf_event_mipsxx.c |  152 +++++++++++++++++++++++++++++++++-
 2 files changed, 155 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 4c9b741..24e07f8 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -81,6 +81,9 @@ struct mips_perf_event {
 #endif
 };
 
+static struct mips_perf_event raw_event;
+static DEFINE_MUTEX(raw_event_mutex);
+
 #define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
 #define C(x) PERF_COUNT_HW_CACHE_##x
 
@@ -96,6 +99,7 @@ struct mips_pmu {
 	void		(*write_counter)(unsigned int idx, unsigned int val);
 	void		(*enable_event)(struct hw_perf_event *evt, int idx);
 	void		(*disable_event)(int idx);
+	const struct mips_perf_event *(*map_raw_event)(u64 config);
 	const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
 	const struct mips_perf_event (*cache_event_map)
 				[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 87103bf..802d98e 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -367,13 +367,20 @@ static int __hw_perf_event_init(struct perf_event *event)
 		pev = mipspmu_map_general_event(event->attr.config);
 	} else if (PERF_TYPE_HW_CACHE == event->attr.type) {
 		pev = mipspmu_map_cache_event(event->attr.config);
+	} else if (PERF_TYPE_RAW == event->attr.type) {
+		/* We are working on the global raw event. */
+		mutex_lock(&raw_event_mutex);
+		pev = mipspmu->map_raw_event(event->attr.config);
 	} else {
 		/* The event type is not (yet) supported. */
 		return -EOPNOTSUPP;
 	}
 
-	if (IS_ERR(pev))
+	if (IS_ERR(pev)) {
+		if (PERF_TYPE_RAW == event->attr.type)
+			mutex_unlock(&raw_event_mutex);
 		return PTR_ERR(pev);
+	}
 
 	/*
 	 * We allow max flexibility on how each individual counter shared
@@ -386,6 +393,8 @@ static int __hw_perf_event_init(struct perf_event *event)
 		check_and_calc_range(event, pev);
 
 	hwc->event_base = mipspmu_perf_event_encode(pev);
+	if (PERF_TYPE_RAW == event->attr.type)
+		mutex_unlock(&raw_event_mutex);
 
 	if (!attr->exclude_user)
 		hwc->config_base |= M_PERFCTL_USER;
@@ -632,6 +641,145 @@ mipsxx_pmu_disable_event(int idx)
 	local_irq_restore(flags);
 }
 
+/* 24K */
+#define IS_UNSUPPORTED_24K_EVENT(r, b)					\
+	((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 ||		\
+	 (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 ||		\
+	 (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 ||		\
+	 (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) ||		\
+	 ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_24K_EVENT(b)					\
+	((b) == 0 || (b) == 1 || (b) == 11)
+
+/* 34K */
+#define IS_UNSUPPORTED_34K_EVENT(r, b)					\
+	((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 ||		\
+	 (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) ||		\
+	 ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_34K_EVENT(b)					\
+	((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_34K_EVENT(r, b)					\
+	((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||		\
+	 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||		\
+	 (r) == 176 || ((b) >= 50 && (b) <= 55) ||			\
+	 ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_34K_EVENT(r)	((r) == 47)
+#endif
+
+/* 74K */
+#define IS_UNSUPPORTED_74K_EVENT(r, b)					\
+	((r) == 5 || ((r) >= 135 && (r) <= 137) ||			\
+	 ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 ||		\
+	 (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) ||		\
+	 (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 ||		\
+	 (b) == 61 || (r) == 62 || (r) == 191 ||			\
+	 ((b) >= 64 && (b) <= 127))
+#define IS_BOTH_COUNTERS_74K_EVENT(b)					\
+	((b) == 0 || (b) == 1)
+
+/* 1004K */
+#define IS_UNSUPPORTED_1004K_EVENT(r, b)				\
+	((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 ||		\
+	 (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_1004K_EVENT(b)					\
+	((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_1004K_EVENT(r, b)					\
+	((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||		\
+	 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||		\
+	 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||	\
+	 (r) == 188 || (b) == 61 || (b) == 62 ||			\
+	 ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_1004K_EVENT(r)	((r) == 47)
+#endif
+
+/*
+ * User can use 0-255 raw events, where 0-127 for the events of even
+ * counters, and 128-255 for odd counters. Note that bit 7 is used to
+ * indicate the parity. So, for example, when user wants to take the
+ * Event Num of 15 for odd counters (by referring to the user manual),
+ * then 128 needs to be added to 15 as the input for the event config,
+ * i.e., 143 (0x8F) to be used.
+ */
+static const struct mips_perf_event *
+mipsxx_pmu_map_raw_event(u64 config)
+{
+	unsigned int raw_id = config & 0xff;
+	unsigned int base_id = raw_id & 0x7f;
+
+	switch (current_cpu_type()) {
+	case CPU_24K:
+		if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
+			return ERR_PTR(-EOPNOTSUPP);
+		raw_event.event_id = base_id;
+		if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
+			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+		else
+			raw_event.cntr_mask =
+				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+		/*
+		 * This is actually doing nothing. Non-multithreading
+		 * CPUs will not check and calculate the range.
+		 */
+		raw_event.range = P;
+#endif
+		break;
+	case CPU_34K:
+		if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
+			return ERR_PTR(-EOPNOTSUPP);
+		raw_event.event_id = base_id;
+		if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
+			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+		else
+			raw_event.cntr_mask =
+				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+		if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
+			raw_event.range = P;
+		else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
+			raw_event.range = V;
+		else
+			raw_event.range = T;
+#endif
+		break;
+	case CPU_74K:
+		if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
+			return ERR_PTR(-EOPNOTSUPP);
+		raw_event.event_id = base_id;
+		if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
+			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+		else
+			raw_event.cntr_mask =
+				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+		raw_event.range = P;
+#endif
+		break;
+	case CPU_1004K:
+		if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
+			return ERR_PTR(-EOPNOTSUPP);
+		raw_event.event_id = base_id;
+		if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
+			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+		else
+			raw_event.cntr_mask =
+				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+		if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
+			raw_event.range = P;
+		else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
+			raw_event.range = V;
+		else
+			raw_event.range = T;
+#endif
+		break;
+	}
+
+	return &raw_event;
+}
+
 static struct mips_pmu mipsxxcore_pmu = {
 	.handle_irq = mipsxx_pmu_handle_irq,
 	.handle_shared_irq = mipsxx_pmu_handle_shared_irq,
@@ -642,6 +790,7 @@ static struct mips_pmu mipsxxcore_pmu = {
 	.write_counter = mipsxx_pmu_write_counter,
 	.enable_event = mipsxx_pmu_enable_event,
 	.disable_event = mipsxx_pmu_disable_event,
+	.map_raw_event = mipsxx_pmu_map_raw_event,
 	.general_event_map = &mipsxxcore_event_map,
 	.cache_event_map = &mipsxxcore_cache_map,
 };
@@ -656,6 +805,7 @@ static struct mips_pmu mipsxx74Kcore_pmu = {
 	.write_counter = mipsxx_pmu_write_counter,
 	.enable_event = mipsxx_pmu_enable_event,
 	.disable_event = mipsxx_pmu_disable_event,
+	.map_raw_event = mipsxx_pmu_map_raw_event,
 	.general_event_map = &mipsxx74Kcore_event_map,
 	.cache_event_map = &mipsxx74Kcore_cache_map,
 };
-- 
1.6.3.3

[PATCH v5 08/12] MIPS: move mipsxx pmu helper functions to Perf-events

[Deng-Cheng Zhu]

This is the 1st patch starting to use Perf-events as the backend of
Oprofile. Here we move pmu helper functions and macros between pmu.h and
perf_event*.c for mipsxx.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/include/asm/pmu.h          |  160 ++--------------------------------
 arch/mips/kernel/perf_event.c        |    2 +
 arch/mips/kernel/perf_event_mipsxx.c |  145 +++++++++++++++++++++++++++++--
 3 files changed, 147 insertions(+), 160 deletions(-)

diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
index 162b24f..2822810 100644
--- a/arch/mips/include/asm/pmu.h
+++ b/arch/mips/include/asm/pmu.h
@@ -8,9 +8,6 @@
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu
  *
- * This file is shared by Oprofile and Perf. It is also shared across the
- * Oprofile implementation for different MIPS CPUs.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -39,160 +36,19 @@
 #define M_PERFCTL_WIDE			(1UL      << 30)
 #define M_PERFCTL_MORE			(1UL      << 31)
 
-#define M_COUNTER_OVERFLOW		(1UL      << 31)
+#define M_PERFCTL_COUNT_EVENT_WHENEVER		\
+	(M_PERFCTL_EXL | M_PERFCTL_KERNEL |	\
+	M_PERFCTL_USER | M_PERFCTL_SUPERVISOR |	\
+	M_PERFCTL_INTERRUPT_ENABLE)
 
 #ifdef CONFIG_MIPS_MT_SMP
-static int cpu_has_mipsmt_pertccounters;
-#define WHAT		(M_TC_EN_VPE | \
-			M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
-/*
- * FIXME: For VSMP, vpe_id() is redefined for Perf, because
- * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. WHAT is not
- * redefined because Perf does not use it.
- */
-#if defined(CONFIG_HW_PERF_EVENTS)
-#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
-			0 : smp_processor_id())
-#else
-#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
-			0 : cpu_data[smp_processor_id()].vpe_id)
-#endif
-/*
- * The number of bits to shift to convert between counters per core and
- * counters per VPE.  There is no reasonable interface atm to obtain the
- * number of VPEs used by Linux and in the 34K this number is fixed to two
- * anyways so we hardcore a few things here for the moment.  The way it's
- * done here will ensure that oprofile VSMP kernel will run right on a lesser
- * core like a 24K also or with maxcpus=1.
- */
-static inline unsigned int vpe_shift(void)
-{
-	if (num_possible_cpus() > 1)
-		return 1;
-
-	return 0;
-}
+#define M_PERFCTL_CONFIG_MASK 0x3fff801f
 #else
-#define WHAT		0
-#define vpe_id()	0
-static inline unsigned int vpe_shift(void)
-{
-	return 0;
-}
+#define M_PERFCTL_CONFIG_MASK 0x1f
 #endif
+#define M_PERFCTL_EVENT_MASK 0xfe0
 
-static inline unsigned int
-counters_total_to_per_cpu(unsigned int counters)
-{
-	return counters >> vpe_shift();
-}
-
-static inline unsigned int
-counters_per_cpu_to_total(unsigned int counters)
-{
-	return counters << vpe_shift();
-}
-
-#define __define_perf_accessors(r, n, np)				\
-									\
-static inline unsigned int r_c0_ ## r ## n(void)			\
-{									\
-	unsigned int cpu = vpe_id();					\
-									\
-	switch (cpu) {							\
-	case 0:								\
-		return read_c0_ ## r ## n();				\
-	case 1:								\
-		return read_c0_ ## r ## np();				\
-	default:							\
-		BUG();							\
-	}								\
-	return 0;							\
-}									\
-									\
-static inline void w_c0_ ## r ## n(unsigned int value)			\
-{									\
-	unsigned int cpu = vpe_id();					\
-									\
-	switch (cpu) {							\
-	case 0:								\
-		write_c0_ ## r ## n(value);				\
-		return;							\
-	case 1:								\
-		write_c0_ ## r ## np(value);				\
-		return;							\
-	default:							\
-		BUG();							\
-	}								\
-	return;								\
-}									\
-
-__define_perf_accessors(perfcntr, 0, 2)
-__define_perf_accessors(perfcntr, 1, 3)
-__define_perf_accessors(perfcntr, 2, 0)
-__define_perf_accessors(perfcntr, 3, 1)
-
-__define_perf_accessors(perfctrl, 0, 2)
-__define_perf_accessors(perfctrl, 1, 3)
-__define_perf_accessors(perfctrl, 2, 0)
-__define_perf_accessors(perfctrl, 3, 1)
-
-static inline int __n_counters(void)
-{
-	if (!(read_c0_config1() & M_CONFIG1_PC))
-		return 0;
-	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
-		return 1;
-	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
-		return 2;
-	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
-		return 3;
-
-	return 4;
-}
-
-static inline int n_counters(void)
-{
-	int counters;
-
-	switch (current_cpu_type()) {
-	case CPU_R10000:
-		counters = 2;
-		break;
-
-	case CPU_R12000:
-	case CPU_R14000:
-		counters = 4;
-		break;
-
-	default:
-		counters = __n_counters();
-	}
-
-	return counters;
-}
-
-static void reset_counters(void *arg)
-{
-	int counters = (int)(long)arg;
-	switch (counters) {
-	case 4:
-		w_c0_perfctrl3(0);
-		w_c0_perfcntr3(0);
-	case 3:
-		w_c0_perfctrl2(0);
-		w_c0_perfcntr2(0);
-	case 2:
-		w_c0_perfctrl1(0);
-		w_c0_perfcntr1(0);
-	case 1:
-		w_c0_perfctrl0(0);
-		w_c0_perfcntr0(0);
-	}
-}
-
-/* Used by Perf */
-#define MIPS_MAX_HWEVENTS 4
+#define M_COUNTER_OVERFLOW		(1UL      << 31)
 
 #elif defined(CONFIG_CPU_RM9000)
 
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 24e07f8..0ef54e6 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -27,6 +27,7 @@
 
 
 #define MAX_PERIOD ((1ULL << 32) - 1)
+#define MIPS_MAX_HWEVENTS 4
 
 struct cpu_hw_events {
 	/* Array of events on this cpu. */
@@ -428,6 +429,7 @@ static int validate_group(struct perf_event *event)
  * specific low-level init routines.
  */
 static int __hw_perf_event_init(struct perf_event *event);
+static void reset_counters(void *arg);
 
 static void hw_perf_event_destroy(struct perf_event *event)
 {
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 802d98e..1c92917 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1,17 +1,146 @@
 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
     defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
 
-#define M_PERFCTL_COUNT_EVENT_WHENEVER		\
-	(M_PERFCTL_EXL | M_PERFCTL_KERNEL |	\
-	M_PERFCTL_USER | M_PERFCTL_SUPERVISOR |	\
-	M_PERFCTL_INTERRUPT_ENABLE)
-
 #ifdef CONFIG_MIPS_MT_SMP
-#define M_PERFCTL_CONFIG_MASK 0x3fff801f
+static int cpu_has_mipsmt_pertccounters;
+/*
+ * FIXME: For VSMP, cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. So
+ * we use smp_processor_id() to identify VPEs.
+ */
+#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
+			0 : smp_processor_id())
+/*
+ * The number of bits to shift to convert between counters per core and
+ * counters per VPE.  There is no reasonable interface atm to obtain the
+ * number of VPEs used by Linux and in the 34K this number is fixed to two
+ * anyways so we hardcore a few things here for the moment.  The way it's
+ * done here will ensure that oprofile VSMP kernel will run right on a lesser
+ * core like a 24K also or with maxcpus=1.
+ */
+static inline unsigned int vpe_shift(void)
+{
+	if (num_possible_cpus() > 1)
+		return 1;
+
+	return 0;
+}
 #else
-#define M_PERFCTL_CONFIG_MASK 0x1f
+#define vpe_id()	0
+static inline unsigned int vpe_shift(void)
+{
+	return 0;
+}
 #endif
-#define M_PERFCTL_EVENT_MASK 0xfe0
+
+static inline unsigned int
+counters_total_to_per_cpu(unsigned int counters)
+{
+	return counters >> vpe_shift();
+}
+
+static inline unsigned int
+counters_per_cpu_to_total(unsigned int counters)
+{
+	return counters << vpe_shift();
+}
+
+#define __define_perf_accessors(r, n, np)				\
+									\
+static inline unsigned int r_c0_ ## r ## n(void)			\
+{									\
+	unsigned int cpu = vpe_id();					\
+									\
+	switch (cpu) {							\
+	case 0:								\
+		return read_c0_ ## r ## n();				\
+	case 1:								\
+		return read_c0_ ## r ## np();				\
+	default:							\
+		BUG();							\
+	}								\
+	return 0;							\
+}									\
+									\
+static inline void w_c0_ ## r ## n(unsigned int value)			\
+{									\
+	unsigned int cpu = vpe_id();					\
+									\
+	switch (cpu) {							\
+	case 0:								\
+		write_c0_ ## r ## n(value);				\
+		return;							\
+	case 1:								\
+		write_c0_ ## r ## np(value);				\
+		return;							\
+	default:							\
+		BUG();							\
+	}								\
+	return;								\
+}									\
+
+__define_perf_accessors(perfcntr, 0, 2)
+__define_perf_accessors(perfcntr, 1, 3)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
+
+__define_perf_accessors(perfctrl, 0, 2)
+__define_perf_accessors(perfctrl, 1, 3)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
+
+static inline int __n_counters(void)
+{
+	if (!(read_c0_config1() & M_CONFIG1_PC))
+		return 0;
+	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
+		return 1;
+	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
+		return 2;
+	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
+		return 3;
+
+	return 4;
+}
+
+static inline int n_counters(void)
+{
+	int counters;
+
+	switch (current_cpu_type()) {
+	case CPU_R10000:
+		counters = 2;
+		break;
+
+	case CPU_R12000:
+	case CPU_R14000:
+		counters = 4;
+		break;
+
+	default:
+		counters = __n_counters();
+	}
+
+	return counters;
+}
+
+static void reset_counters(void *arg)
+{
+	int counters = (int)(long)arg;
+	switch (counters) {
+	case 4:
+		w_c0_perfctrl3(0);
+		w_c0_perfcntr3(0);
+	case 3:
+		w_c0_perfctrl2(0);
+		w_c0_perfcntr2(0);
+	case 2:
+		w_c0_perfctrl1(0);
+		w_c0_perfcntr1(0);
+	case 1:
+		w_c0_perfctrl0(0);
+		w_c0_perfcntr0(0);
+	}
+}
 
 static inline unsigned int
 mipsxx_pmu_read_counter(unsigned int idx)
-- 
1.6.3.3

[PATCH v5 09/12] MIPS/Perf-events: replace pmu names with numeric IDs

[Deng-Cheng Zhu]

Using Perf-events as the backend, clients such as Oprofile will need to
enquire the pmu names. A convenient way to do this is to use pmu id to
index the exported name array. And this is what we are doing here.

NOTE: While using scripts/checkpatch.pl to check this patch, a style
warning is reported. I suppose it is a false positive, and will report to
the maintainer. The message is:
=======================================
WARNING:
EXPORT_SYMBOL(foo); should immediately follow its function/variable
#81: FILE: arch/mips/kernel/perf_event.c:112:
+EXPORT_SYMBOL_GPL(mips_pmu_names);
=======================================

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/include/asm/pmu.h          |   26 ++++++++++++++++++++++++++
 arch/mips/kernel/perf_event.c        |   31 ++++++++++++++++++++++++++++++-
 arch/mips/kernel/perf_event_mipsxx.c |   12 +++++++-----
 3 files changed, 63 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
index 2822810..16d4fcd 100644
--- a/arch/mips/include/asm/pmu.h
+++ b/arch/mips/include/asm/pmu.h
@@ -89,4 +89,30 @@ extern unsigned int rm9000_perfcount_irq;
 
 #endif /* CONFIG_CPU_* */
 
+/* MIPS PMU IDs for use by internal perf clients. */
+enum mips_pmu_id {
+	/* mipsxx */
+	MIPS_PMU_ID_20K = 0,
+	MIPS_PMU_ID_24K,
+	MIPS_PMU_ID_25K,
+	MIPS_PMU_ID_1004K,
+	MIPS_PMU_ID_34K,
+	MIPS_PMU_ID_74K,
+	MIPS_PMU_ID_5K,
+	MIPS_PMU_ID_R10000V2,
+	MIPS_PMU_ID_R10000,
+	MIPS_PMU_ID_R12000,
+	MIPS_PMU_ID_SB1,
+	/* rm9000 */
+	MIPS_PMU_ID_RM9000,
+	/* loongson2 */
+	MIPS_PMU_ID_LOONGSON2,
+	/* unsupported */
+	MIPS_PMU_ID_UNSUPPORTED,
+};
+
+extern const char *mips_pmu_names[];
+
+extern enum mips_pmu_id mipspmu_get_pmu_id(void);
+
 #endif /* __MIPS_PMU_H__ */
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 0ef54e6..f05e2b1 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -88,8 +88,31 @@ static DEFINE_MUTEX(raw_event_mutex);
 #define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
 #define C(x) PERF_COUNT_HW_CACHE_##x
 
+/* MIPS PMU names */
+const char *mips_pmu_names[] = {
+	/* mipsxx */
+	[MIPS_PMU_ID_20K]		= "mips/20K",
+	[MIPS_PMU_ID_24K]		= "mips/24K",
+	[MIPS_PMU_ID_25K]		= "mips/25K",
+	[MIPS_PMU_ID_1004K]		= "mips/1004K",
+	[MIPS_PMU_ID_34K]		= "mips/34K",
+	[MIPS_PMU_ID_74K]		= "mips/74K",
+	[MIPS_PMU_ID_5K]		= "mips/5K",
+	[MIPS_PMU_ID_R10000V2]		= "mips/r10000-v2.x",
+	[MIPS_PMU_ID_R10000]		= "mips/r10000",
+	[MIPS_PMU_ID_R12000]		= "mips/r12000",
+	[MIPS_PMU_ID_SB1]		= "mips/sb1",
+	/* rm9000 */
+	[MIPS_PMU_ID_RM9000]		= "mips/rm9000",
+	/* loongson2 */
+	[MIPS_PMU_ID_LOONGSON2]		= "mips/loongson2",
+	/* unsupported */
+	[MIPS_PMU_ID_UNSUPPORTED]	= NULL,
+};
+EXPORT_SYMBOL_GPL(mips_pmu_names);
+
 struct mips_pmu {
-	const char	*name;
+	enum mips_pmu_id id;
 	irqreturn_t	(*handle_irq)(int irq, void *dev);
 	int		(*handle_shared_irq)(void);
 	void		(*start)(void);
@@ -111,6 +134,12 @@ struct mips_pmu {
 
 static const struct mips_pmu *mipspmu;
 
+enum mips_pmu_id mipspmu_get_pmu_id(void)
+{
+	return mipspmu ? mipspmu->id : MIPS_PMU_ID_UNSUPPORTED;
+}
+EXPORT_SYMBOL_GPL(mipspmu_get_pmu_id);
+
 static int
 mipspmu_event_set_period(struct perf_event *event,
 			struct hw_perf_event *hwc,
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 1c92917..4e37a3a 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -962,22 +962,22 @@ init_hw_perf_events(void)
 
 	switch (current_cpu_type()) {
 	case CPU_24K:
-		mipsxxcore_pmu.name = "mips/24K";
+		mipsxxcore_pmu.id = MIPS_PMU_ID_24K;
 		mipsxxcore_pmu.num_counters = counters;
 		mipspmu = &mipsxxcore_pmu;
 		break;
 	case CPU_34K:
-		mipsxxcore_pmu.name = "mips/34K";
+		mipsxxcore_pmu.id = MIPS_PMU_ID_34K;
 		mipsxxcore_pmu.num_counters = counters;
 		mipspmu = &mipsxxcore_pmu;
 		break;
 	case CPU_74K:
-		mipsxx74Kcore_pmu.name = "mips/74K";
+		mipsxx74Kcore_pmu.id = MIPS_PMU_ID_74K;
 		mipsxx74Kcore_pmu.num_counters = counters;
 		mipspmu = &mipsxx74Kcore_pmu;
 		break;
 	case CPU_1004K:
-		mipsxxcore_pmu.name = "mips/1004K";
+		mipsxxcore_pmu.id = MIPS_PMU_ID_1004K;
 		mipsxxcore_pmu.num_counters = counters;
 		mipspmu = &mipsxxcore_pmu;
 		break;
@@ -989,7 +989,9 @@ init_hw_perf_events(void)
 
 	if (mipspmu)
 		pr_cont("%s PMU enabled, %d counters available to each "
-			"CPU\n", mipspmu->name, mipspmu->num_counters);
+			"CPU\n",
+			mips_pmu_names[mipspmu->id],
+			mipspmu->num_counters);
 
 	return 0;
 }
-- 
1.6.3.3

[PATCH v5 10/12] MIPS/Perf-events: allow modules to get pmu number of counters

[Deng-Cheng Zhu]

Oprofile module needs a function to get the number of pmu counters in its
high level interfaces.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/include/asm/pmu.h   |    1 +
 arch/mips/kernel/perf_event.c |    6 ++++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
index 16d4fcd..023a915 100644
--- a/arch/mips/include/asm/pmu.h
+++ b/arch/mips/include/asm/pmu.h
@@ -114,5 +114,6 @@ enum mips_pmu_id {
 extern const char *mips_pmu_names[];
 
 extern enum mips_pmu_id mipspmu_get_pmu_id(void);
+extern int mipspmu_get_max_events(void);
 
 #endif /* __MIPS_PMU_H__ */
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index f05e2b1..dc3a553 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -140,6 +140,12 @@ enum mips_pmu_id mipspmu_get_pmu_id(void)
 }
 EXPORT_SYMBOL_GPL(mipspmu_get_pmu_id);
 
+int mipspmu_get_max_events(void)
+{
+	return mipspmu ? mipspmu->num_counters : 0;
+}
+EXPORT_SYMBOL_GPL(mipspmu_get_max_events);
+
 static int
 mipspmu_event_set_period(struct perf_event *event,
 			struct hw_perf_event *hwc,
-- 
1.6.3.3

[PATCH v5 11/12] MIPS/Oprofile: use Perf-events framework as backend

[Deng-Cheng Zhu]

This patch is based on Will Deacon's work for ARM. The well-written
reasons and ideas can be found here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-April/013210.html

This effort makes the bug-fixes shared by different pmu users/clients
(for now, Oprofile & Perf-events), and make them coexist in the system
without lock issues, and make their results comparable.

So this patch moves Oprofile on top of Perf-events by replacing its
original interfaces with new ones calling Perf-events.

Oprofile uses raw events, so Perf-events (mipsxx in this patch) is
modified to support more mipsxx CPUs.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/kernel/perf_event.c        |    7 +-
 arch/mips/kernel/perf_event_mipsxx.c |  125 ++++++++++++------
 arch/mips/oprofile/common.c          |  237 +++++++++++++++++++++++++---------
 3 files changed, 266 insertions(+), 103 deletions(-)

diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index dc3a553..f3bb2f9 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -390,6 +390,9 @@ mipspmu_map_general_event(int idx)
 {
 	const struct mips_perf_event *pev;
 
+	if (!mipspmu->general_event_map)
+		return ERR_PTR(-EOPNOTSUPP);
+
 	pev = ((*mipspmu->general_event_map)[idx].event_id ==
 		UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
 		&(*mipspmu->general_event_map)[idx]);
@@ -415,6 +418,9 @@ mipspmu_map_cache_event(u64 config)
 	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 		return ERR_PTR(-EINVAL);
 
+	if (!mipspmu->cache_event_map)
+		return ERR_PTR(-EOPNOTSUPP);
+
 	pev = &((*mipspmu->cache_event_map)
 					[cache_type]
 					[cache_op]
@@ -424,7 +430,6 @@ mipspmu_map_cache_event(u64 config)
 		return ERR_PTR(-EOPNOTSUPP);
 
 	return pev;
-
 }
 
 static int validate_event(struct cpu_hw_events *cpuc,
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 4e37a3a..aa8f5f9 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -904,39 +904,36 @@ mipsxx_pmu_map_raw_event(u64 config)
 			raw_event.range = T;
 #endif
 		break;
+	case CPU_20KC:
+	case CPU_25KF:
+	case CPU_5KC:
+	case CPU_R10000:
+	case CPU_R12000:
+	case CPU_R14000:
+	case CPU_SB1:
+	case CPU_SB1A:
+		raw_event.event_id = base_id;
+		raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+		raw_event.range = P;
+#endif
+		break;
 	}
 
 	return &raw_event;
 }
 
 static struct mips_pmu mipsxxcore_pmu = {
-	.handle_irq = mipsxx_pmu_handle_irq,
-	.handle_shared_irq = mipsxx_pmu_handle_shared_irq,
-	.start = mipsxx_pmu_start,
-	.stop = mipsxx_pmu_stop,
-	.alloc_counter = mipsxx_pmu_alloc_counter,
-	.read_counter = mipsxx_pmu_read_counter,
-	.write_counter = mipsxx_pmu_write_counter,
-	.enable_event = mipsxx_pmu_enable_event,
-	.disable_event = mipsxx_pmu_disable_event,
-	.map_raw_event = mipsxx_pmu_map_raw_event,
-	.general_event_map = &mipsxxcore_event_map,
-	.cache_event_map = &mipsxxcore_cache_map,
-};
-
-static struct mips_pmu mipsxx74Kcore_pmu = {
-	.handle_irq = mipsxx_pmu_handle_irq,
-	.handle_shared_irq = mipsxx_pmu_handle_shared_irq,
-	.start = mipsxx_pmu_start,
-	.stop = mipsxx_pmu_stop,
-	.alloc_counter = mipsxx_pmu_alloc_counter,
-	.read_counter = mipsxx_pmu_read_counter,
-	.write_counter = mipsxx_pmu_write_counter,
-	.enable_event = mipsxx_pmu_enable_event,
-	.disable_event = mipsxx_pmu_disable_event,
-	.map_raw_event = mipsxx_pmu_map_raw_event,
-	.general_event_map = &mipsxx74Kcore_event_map,
-	.cache_event_map = &mipsxx74Kcore_cache_map,
+	.handle_irq		= mipsxx_pmu_handle_irq,
+	.handle_shared_irq	= mipsxx_pmu_handle_shared_irq,
+	.start			= mipsxx_pmu_start,
+	.stop			= mipsxx_pmu_stop,
+	.alloc_counter		= mipsxx_pmu_alloc_counter,
+	.read_counter		= mipsxx_pmu_read_counter,
+	.write_counter		= mipsxx_pmu_write_counter,
+	.enable_event		= mipsxx_pmu_enable_event,
+	.disable_event		= mipsxx_pmu_disable_event,
+	.map_raw_event		= mipsxx_pmu_map_raw_event,
 };
 
 static int __init
@@ -963,35 +960,77 @@ init_hw_perf_events(void)
 	switch (current_cpu_type()) {
 	case CPU_24K:
 		mipsxxcore_pmu.id = MIPS_PMU_ID_24K;
-		mipsxxcore_pmu.num_counters = counters;
-		mipspmu = &mipsxxcore_pmu;
+		mipsxxcore_pmu.general_event_map = &mipsxxcore_event_map;
+		mipsxxcore_pmu.cache_event_map = &mipsxxcore_cache_map;
 		break;
 	case CPU_34K:
 		mipsxxcore_pmu.id = MIPS_PMU_ID_34K;
-		mipsxxcore_pmu.num_counters = counters;
-		mipspmu = &mipsxxcore_pmu;
+		mipsxxcore_pmu.general_event_map = &mipsxxcore_event_map;
+		mipsxxcore_pmu.cache_event_map = &mipsxxcore_cache_map;
 		break;
 	case CPU_74K:
-		mipsxx74Kcore_pmu.id = MIPS_PMU_ID_74K;
-		mipsxx74Kcore_pmu.num_counters = counters;
-		mipspmu = &mipsxx74Kcore_pmu;
+		mipsxxcore_pmu.id = MIPS_PMU_ID_74K;
+		mipsxxcore_pmu.general_event_map = &mipsxx74Kcore_event_map;
+		mipsxxcore_pmu.cache_event_map = &mipsxx74Kcore_cache_map;
 		break;
 	case CPU_1004K:
 		mipsxxcore_pmu.id = MIPS_PMU_ID_1004K;
-		mipsxxcore_pmu.num_counters = counters;
-		mipspmu = &mipsxxcore_pmu;
+		mipsxxcore_pmu.general_event_map = &mipsxxcore_event_map;
+		mipsxxcore_pmu.cache_event_map = &mipsxxcore_cache_map;
+		break;
+	/*
+	 * To make perf events fully supported for the following cores,
+	 * we need to fill out the general event map and the cache event
+	 * map. Before that, raw events are supported on these cores.
+	 * Note that the raw events for these cores do not go through the
+	 * accurate check in mipsxx_pmu_map_raw_event(), but they can make
+	 * the perf events the backend of perf clients such as Oprofile.
+	 */
+	case CPU_20KC:
+		mipsxxcore_pmu.id = MIPS_PMU_ID_20K;
+		mipsxxcore_pmu.general_event_map = NULL;
+		mipsxxcore_pmu.cache_event_map = NULL;
+		break;
+	case CPU_25KF:
+		mipsxxcore_pmu.id = MIPS_PMU_ID_25K;
+		mipsxxcore_pmu.general_event_map = NULL;
+		mipsxxcore_pmu.cache_event_map = NULL;
+		break;
+	case CPU_5KC:
+		mipsxxcore_pmu.id = MIPS_PMU_ID_5K;
+		mipsxxcore_pmu.general_event_map = NULL;
+		mipsxxcore_pmu.cache_event_map = NULL;
+		break;
+	case CPU_R10000:
+		if ((current_cpu_data.processor_id & 0xff) == 0x20)
+			mipsxxcore_pmu.id = MIPS_PMU_ID_R10000V2;
+		else
+			mipsxxcore_pmu.id = MIPS_PMU_ID_R10000;
+
+		mipsxxcore_pmu.general_event_map = NULL;
+		mipsxxcore_pmu.cache_event_map = NULL;
+		break;
+	case CPU_R12000:
+	case CPU_R14000:
+		mipsxxcore_pmu.id = MIPS_PMU_ID_R12000;
+		mipsxxcore_pmu.general_event_map = NULL;
+		mipsxxcore_pmu.cache_event_map = NULL;
+		break;
+	case CPU_SB1:
+	case CPU_SB1A:
+		mipsxxcore_pmu.id = MIPS_PMU_ID_SB1;
+		mipsxxcore_pmu.general_event_map = NULL;
+		mipsxxcore_pmu.cache_event_map = NULL;
 		break;
 	default:
-		pr_cont("Either hardware does not support performance "
-			"counters, or not yet implemented.\n");
+		pr_cont("Perf events unsupported for this CPU.\n");
 		return -ENODEV;
 	}
+	mipsxxcore_pmu.num_counters = counters;
+	mipspmu = &mipsxxcore_pmu;
 
-	if (mipspmu)
-		pr_cont("%s PMU enabled, %d counters available to each "
-			"CPU\n",
-			mips_pmu_names[mipspmu->id],
-			mipspmu->num_counters);
+	pr_cont("%s PMU enabled, %d counters available to each "
+		"CPU\n", mips_pmu_names[mipspmu->id], mipspmu->num_counters);
 
 	return 0;
 }
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index f9eb1ab..673745d 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -5,40 +5,160 @@
  *
  * Copyright (C) 2004, 2005 Ralf Baechle
  * Copyright (C) 2005 MIPS Technologies, Inc.
+ * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu (Using perf
+ * events as the backend of Oprofile. This is mainly based on the idea and
+ * the code for ARM.)
  */
 #include <linux/compiler.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/oprofile.h>
 #include <linux/smp.h>
+#include <linux/cpumask.h>
+#include <linux/perf_event.h>
+#include <linux/slab.h>
 #include <asm/cpu-info.h>
+#include <asm/pmu.h>
+
+#ifdef CONFIG_HW_PERF_EVENTS
+/* Per-counter configuration as set via oprofilefs.  */
+struct op_counter_config {
+	unsigned long enabled;
+	unsigned long event;
+	unsigned long count;
+	/* Dummies because I am too lazy to hack the userspace tools.  */
+	unsigned long kernel;
+	unsigned long user;
+	unsigned long exl;
+	unsigned long unit_mask;
+	struct perf_event_attr attr;
+};
+static struct op_counter_config ctr[20];
+static struct perf_event **perf_events[nr_cpumask_bits];
+static int perf_num_counters;
 
-#include "op_impl.h"
+/*
+ * Overflow callback for oprofile.
+ */
+static void op_overflow_handler(struct perf_event *event, int unused,
+		struct perf_sample_data *data, struct pt_regs *regs)
+{
+	int id;
+	u32 cpu = smp_processor_id();
+
+	for (id = 0; id < perf_num_counters; ++id)
+		if (perf_events[cpu][id] == event)
+			break;
+
+	if (id != perf_num_counters)
+		oprofile_add_sample(regs, id);
+	else
+		pr_warning("oprofile: ignoring spurious overflow "
+			"on cpu %u\n", cpu);
+}
 
-extern struct op_mips_model op_model_mipsxx_ops __weak;
-extern struct op_mips_model op_model_rm9000_ops __weak;
-extern struct op_mips_model op_model_loongson2_ops __weak;
+/*
+ * Attributes are created as "pinned" events and so are permanently
+ * scheduled on the PMU.
+ */
+static void op_perf_setup(void)
+{
+	int i;
+	u32 size = sizeof(struct perf_event_attr);
+	struct perf_event_attr *attr;
+
+	for (i = 0; i < perf_num_counters; ++i) {
+		attr = &ctr[i].attr;
+		memset(attr, 0, size);
+		attr->type		= PERF_TYPE_RAW;
+		attr->size		= size;
+		attr->config		= ctr[i].event + (i & 0x1 ? 128 : 0);
+		attr->sample_period	= ctr[i].count;
+		attr->pinned		= 1;
+		/*
+		 * Only exclude_user/exclude_kernel/exclude_hv are defined
+		 * in perf_event_attr, maybe we can use exclude_hv for exl.
+		 * But user space perf/oprofile tools need to get agreement.
+		 */
+		if (!ctr[i].user)
+			attr->exclude_user = 1;
+		if (!ctr[i].kernel && !ctr[i].exl)
+			attr->exclude_kernel = 1;
+	}
+}
 
-static struct op_mips_model *model;
+static int op_create_counter(int cpu, int event)
+{
+	int ret = 0;
+	struct perf_event *pevent;
+
+	if (!ctr[event].enabled || (perf_events[cpu][event] != NULL))
+		return ret;
+
+	pevent = perf_event_create_kernel_counter(&ctr[event].attr,
+						  cpu, -1,
+						  op_overflow_handler);
+
+	if (IS_ERR(pevent)) {
+		ret = PTR_ERR(pevent);
+	} else if (pevent->state != PERF_EVENT_STATE_ACTIVE) {
+		pr_warning("oprofile: failed to enable event %d "
+			"on CPU %d (state %d)\n", event, cpu, pevent->state);
+		ret = -EBUSY;
+	} else {
+		perf_events[cpu][event] = pevent;
+	}
 
-static struct op_counter_config ctr[20];
+	return ret;
+}
 
-static int op_mips_setup(void)
+static void op_destroy_counter(int cpu, int event)
+{
+	struct perf_event *pevent = perf_events[cpu][event];
+
+	if (pevent) {
+		perf_event_release_kernel(pevent);
+		perf_events[cpu][event] = NULL;
+	}
+}
+
+static int op_perf_start(void)
 {
-	/* Pre-compute the values to stuff in the hardware registers.  */
-	model->reg_setup(ctr);
+	int cpu, event, ret = 0;
+
+	for_each_online_cpu(cpu) {
+		for (event = 0; event < perf_num_counters; ++event) {
+			ret = op_create_counter(cpu, event);
+			if (ret)
+				goto out;
+		}
+	}
+
+out:
+	return ret;
+}
 
-	/* Configure the registers on all cpus.  */
-	on_each_cpu(model->cpu_setup, NULL, 1);
+static void op_perf_stop(void)
+{
+	int cpu, event;
 
-        return 0;
+	for_each_online_cpu(cpu)
+		for (event = 0; event < perf_num_counters; ++event)
+			op_destroy_counter(cpu, event);
+}
+
+static int op_mips_setup(void)
+{
+	op_perf_setup();
+
+	return 0;
 }
 
 static int op_mips_create_files(struct super_block *sb, struct dentry *root)
 {
 	int i;
 
-	for (i = 0; i < model->num_counters; ++i) {
+	for (i = 0; i < perf_num_counters; ++i) {
 		struct dentry *dir;
 		char buf[4];
 
@@ -60,70 +180,69 @@ static int op_mips_create_files(struct super_block *sb, struct dentry *root)
 
 static int op_mips_start(void)
 {
-	on_each_cpu(model->cpu_start, NULL, 1);
-
-	return 0;
+	return op_perf_start();
 }
 
 static void op_mips_stop(void)
 {
-	/* Disable performance monitoring for all counters.  */
-	on_each_cpu(model->cpu_stop, NULL, 1);
+	op_perf_stop();
 }
 
 int __init oprofile_arch_init(struct oprofile_operations *ops)
 {
-	struct op_mips_model *lmodel = NULL;
-	int res;
-
-	switch (current_cpu_type()) {
-	case CPU_5KC:
-	case CPU_20KC:
-	case CPU_24K:
-	case CPU_25KF:
-	case CPU_34K:
-	case CPU_1004K:
-	case CPU_74K:
-	case CPU_SB1:
-	case CPU_SB1A:
-	case CPU_R10000:
-	case CPU_R12000:
-	case CPU_R14000:
-		lmodel = &op_model_mipsxx_ops;
-		break;
-
-	case CPU_RM9000:
-		lmodel = &op_model_rm9000_ops;
-		break;
-	case CPU_LOONGSON2:
-		lmodel = &op_model_loongson2_ops;
-		break;
-	};
-
-	if (!lmodel)
-		return -ENODEV;
-
-	res = lmodel->init();
-	if (res)
-		return res;
-
-	model = lmodel;
+	int cpu;
+
+	perf_num_counters = mipspmu_get_max_events();
+
+	for_each_possible_cpu(cpu) {
+		perf_events[cpu] = kcalloc(perf_num_counters,
+				sizeof(struct perf_event *), GFP_KERNEL);
+		if (!perf_events[cpu]) {
+			pr_info("oprofile: failed to allocate %d perf events "
+				"for cpu %d\n", perf_num_counters, cpu);
+			while (--cpu >= 0)
+				kfree(perf_events[cpu]);
+			return -ENOMEM;
+		}
+	}
 
 	ops->create_files	= op_mips_create_files;
 	ops->setup		= op_mips_setup;
-	//ops->shutdown         = op_mips_shutdown;
+	ops->shutdown		= op_mips_stop;
 	ops->start		= op_mips_start;
 	ops->stop		= op_mips_stop;
-	ops->cpu_type		= lmodel->cpu_type;
+	ops->cpu_type		= (char *)mips_pmu_names[mipspmu_get_pmu_id()];
 
-	printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
-	       lmodel->cpu_type);
+	if (!ops->cpu_type)
+		return -ENODEV;
+	else
+		pr_info("oprofile: using %s performance monitoring.\n",
+			ops->cpu_type);
 
 	return 0;
 }
 
 void oprofile_arch_exit(void)
 {
-	if (model)
-		model->exit();
+	int cpu, id;
+	struct perf_event *event;
+
+	if (*perf_events) {
+		for_each_possible_cpu(cpu) {
+			for (id = 0; id < perf_num_counters; ++id) {
+				event = perf_events[cpu][id];
+				if (event)
+					perf_event_release_kernel(event);
+			}
+			kfree(perf_events[cpu]);
+		}
+	}
+}
+#else
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+	pr_info("oprofile: hardware counters not available\n");
+	return -ENODEV;
 }
+void oprofile_arch_exit(void) {}
+#endif /* CONFIG_HW_PERF_EVENTS */
-- 
1.6.3.3

[PATCH v5 12/12] MIPS/Oprofile: remove old files and update Kconfig/Makefile

[Deng-Cheng Zhu]

Now that Oprofile uses Perf-events as backend, its old framework files
are not needed. Kconfig is modified to let hardware performance events be
the prerequisite of Oprofile.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
---
 arch/mips/Kconfig                       |    4 +-
 arch/mips/oprofile/Makefile             |    7 -
 arch/mips/oprofile/op_impl.h            |   39 -----
 arch/mips/oprofile/op_model_loongson2.c |  139 ------------------
 arch/mips/oprofile/op_model_mipsxx.c    |  237 -------------------------------
 arch/mips/oprofile/op_model_rm9000.c    |  124 ----------------
 6 files changed, 2 insertions(+), 548 deletions(-)
 delete mode 100644 arch/mips/oprofile/op_impl.h
 delete mode 100644 arch/mips/oprofile/op_model_loongson2.c
 delete mode 100644 arch/mips/oprofile/op_model_mipsxx.c
 delete mode 100644 arch/mips/oprofile/op_model_rm9000.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 27577b4..6f47117 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3,7 +3,7 @@ config MIPS
 	default y
 	select HAVE_GENERIC_DMA_COHERENT
 	select HAVE_IDE
-	select HAVE_OPROFILE
+	select HAVE_OPROFILE if HW_PERF_EVENTS
 	select HAVE_PERF_EVENTS
 	select PERF_USE_VMALLOC
 	select GENERIC_ATOMIC64 if !64BIT
@@ -1890,7 +1890,7 @@ config NODES_SHIFT
 
 config HW_PERF_EVENTS
 	bool "Enable hardware performance counter support for perf events"
-	depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
+	depends on PERF_EVENTS && !MIPS_MT_SMTC
 	default y
 	help
 	  Enable hardware performance counter support for perf events. If
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 02cc65e..10ec71d 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -9,10 +9,3 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
 		timer_int.o )
 
 oprofile-y				:= $(DRIVER_OBJS) common.o
-
-oprofile-$(CONFIG_CPU_MIPS32)		+= op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_MIPS64)		+= op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_R10000)		+= op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_SB1)		+= op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_RM9000)		+= op_model_rm9000.o
-oprofile-$(CONFIG_CPU_LOONGSON2)	+= op_model_loongson2.o
diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h
deleted file mode 100644
index f04b54f..0000000
--- a/arch/mips/oprofile/op_impl.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/**
- * @file arch/alpha/oprofile/op_impl.h
- *
- * @remark Copyright 2002 OProfile authors
- * @remark Read the file COPYING
- *
- * @author Richard Henderson <rth@twiddle.net>
- */
-
-#ifndef OP_IMPL_H
-#define OP_IMPL_H 1
-
-extern int (*perf_irq)(void);
-
-/* Per-counter configuration as set via oprofilefs.  */
-struct op_counter_config {
-	unsigned long enabled;
-	unsigned long event;
-	unsigned long count;
-	/* Dummies because I am too lazy to hack the userspace tools.  */
-	unsigned long kernel;
-	unsigned long user;
-	unsigned long exl;
-	unsigned long unit_mask;
-};
-
-/* Per-architecture configury and hooks.  */
-struct op_mips_model {
-	void (*reg_setup) (struct op_counter_config *);
-	void (*cpu_setup) (void *dummy);
-	int (*init)(void);
-	void (*exit)(void);
-	void (*cpu_start)(void *args);
-	void (*cpu_stop)(void *args);
-	char *cpu_type;
-	unsigned char num_counters;
-};
-
-#endif
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
deleted file mode 100644
index 9e61ecd..0000000
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Loongson2 performance counter driver for oprofile
- *
- * Copyright (C) 2009 Lemote Inc.
- * Author: Yanhua <yanh@lemote.com>
- * Author: Wu Zhangjin <wuzhangjin@gmail.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/oprofile.h>
-#include <linux/interrupt.h>
-#include <asm/pmu.h>
-
-#include <loongson.h>			/* LOONGSON2_PERFCNT_IRQ */
-#include "op_impl.h"
-
-static struct loongson2_register_config {
-	unsigned int ctrl;
-	unsigned long long reset_counter1;
-	unsigned long long reset_counter2;
-	int cnt1_enabled, cnt2_enabled;
-} reg;
-
-static char *oprofid = "LoongsonPerf";
-static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
-
-static void loongson2_reg_setup(struct op_counter_config *cfg)
-{
-	unsigned int ctrl = 0;
-
-	reg.reset_counter1 = 0;
-	reg.reset_counter2 = 0;
-
-	/*
-	 * Compute the performance counter ctrl word.
-	 * For now, count kernel and user mode.
-	 */
-	if (cfg[0].enabled) {
-		ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
-		reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
-	}
-
-	if (cfg[1].enabled) {
-		ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
-		reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
-	}
-
-	if (cfg[0].enabled || cfg[1].enabled) {
-		ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE;
-		if (cfg[0].kernel || cfg[1].kernel)
-			ctrl |= LOONGSON2_PERFCTRL_KERNEL;
-		if (cfg[0].user || cfg[1].user)
-			ctrl |= LOONGSON2_PERFCTRL_USER;
-	}
-
-	reg.ctrl = ctrl;
-
-	reg.cnt1_enabled = cfg[0].enabled;
-	reg.cnt2_enabled = cfg[1].enabled;
-}
-
-static void loongson2_cpu_setup(void *args)
-{
-	write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1);
-}
-
-static void loongson2_cpu_start(void *args)
-{
-	/* Start all counters on current CPU */
-	if (reg.cnt1_enabled || reg.cnt2_enabled)
-		write_c0_perfctrl(reg.ctrl);
-}
-
-static void loongson2_cpu_stop(void *args)
-{
-	/* Stop all counters on current CPU */
-	write_c0_perfctrl(0);
-	memset(&reg, 0, sizeof(reg));
-}
-
-static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
-{
-	uint64_t counter, counter1, counter2;
-	struct pt_regs *regs = get_irq_regs();
-	int enabled;
-
-	/* Check whether the irq belongs to me */
-	enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
-	if (!enabled)
-		return IRQ_NONE;
-	enabled = reg.cnt1_enabled | reg.cnt2_enabled;
-	if (!enabled)
-		return IRQ_NONE;
-
-	counter = read_c0_perfcnt();
-	counter1 = counter & 0xffffffff;
-	counter2 = counter >> 32;
-
-	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
-		if (reg.cnt1_enabled)
-			oprofile_add_sample(regs, 0);
-		counter1 = reg.reset_counter1;
-	}
-	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
-		if (reg.cnt2_enabled)
-			oprofile_add_sample(regs, 1);
-		counter2 = reg.reset_counter2;
-	}
-
-	write_c0_perfcnt((counter2 << 32) | counter1);
-
-	return IRQ_HANDLED;
-}
-
-static int __init loongson2_init(void)
-{
-	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
-			   IRQF_SHARED, "Perfcounter", oprofid);
-}
-
-static void loongson2_exit(void)
-{
-	write_c0_perfctrl(0);
-	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
-}
-
-struct op_mips_model op_model_loongson2_ops = {
-	.reg_setup = loongson2_reg_setup,
-	.cpu_setup = loongson2_cpu_setup,
-	.init = loongson2_init,
-	.exit = loongson2_exit,
-	.cpu_start = loongson2_cpu_start,
-	.cpu_stop = loongson2_cpu_stop,
-	.cpu_type = LOONGSON2_CPU_TYPE,
-	.num_counters = 2
-};
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
deleted file mode 100644
index 96f14e8..0000000
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004, 05, 06 by Ralf Baechle
- * Copyright (C) 2005 by MIPS Technologies, Inc.
- */
-#include <linux/cpumask.h>
-#include <linux/oprofile.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <asm/irq_regs.h>
-#include <asm/pmu.h>
-
-#include "op_impl.h"
-
-
-struct op_mips_model op_model_mipsxx_ops;
-
-static struct mipsxx_register_config {
-	unsigned int control[4];
-	unsigned int counter[4];
-} reg;
-
-/* Compute all of the registers in preparation for enabling profiling.  */
-
-static void mipsxx_reg_setup(struct op_counter_config *ctr)
-{
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
-	int i;
-
-	/* Compute the performance counter control word.  */
-	for (i = 0; i < counters; i++) {
-		reg.control[i] = 0;
-		reg.counter[i] = 0;
-
-		if (!ctr[i].enabled)
-			continue;
-
-		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
-		                 M_PERFCTL_INTERRUPT_ENABLE;
-		if (ctr[i].kernel)
-			reg.control[i] |= M_PERFCTL_KERNEL;
-		if (ctr[i].user)
-			reg.control[i] |= M_PERFCTL_USER;
-		if (ctr[i].exl)
-			reg.control[i] |= M_PERFCTL_EXL;
-		reg.counter[i] = 0x80000000 - ctr[i].count;
-	}
-}
-
-/* Program all of the registers in preparation for enabling profiling.  */
-
-static void mipsxx_cpu_setup(void *args)
-{
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
-
-	switch (counters) {
-	case 4:
-		w_c0_perfctrl3(0);
-		w_c0_perfcntr3(reg.counter[3]);
-	case 3:
-		w_c0_perfctrl2(0);
-		w_c0_perfcntr2(reg.counter[2]);
-	case 2:
-		w_c0_perfctrl1(0);
-		w_c0_perfcntr1(reg.counter[1]);
-	case 1:
-		w_c0_perfctrl0(0);
-		w_c0_perfcntr0(reg.counter[0]);
-	}
-}
-
-/* Start all counters on current CPU */
-static void mipsxx_cpu_start(void *args)
-{
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
-
-	switch (counters) {
-	case 4:
-		w_c0_perfctrl3(WHAT | reg.control[3]);
-	case 3:
-		w_c0_perfctrl2(WHAT | reg.control[2]);
-	case 2:
-		w_c0_perfctrl1(WHAT | reg.control[1]);
-	case 1:
-		w_c0_perfctrl0(WHAT | reg.control[0]);
-	}
-}
-
-/* Stop all counters on current CPU */
-static void mipsxx_cpu_stop(void *args)
-{
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
-
-	switch (counters) {
-	case 4:
-		w_c0_perfctrl3(0);
-	case 3:
-		w_c0_perfctrl2(0);
-	case 2:
-		w_c0_perfctrl1(0);
-	case 1:
-		w_c0_perfctrl0(0);
-	}
-}
-
-static int mipsxx_perfcount_handler(void)
-{
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
-	unsigned int control;
-	unsigned int counter;
-	int handled = IRQ_NONE;
-
-	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
-		return handled;
-
-	switch (counters) {
-#define HANDLE_COUNTER(n)						\
-	case n + 1:							\
-		control = r_c0_perfctrl ## n();				\
-		counter = r_c0_perfcntr ## n();				\
-		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
-		    (counter & M_COUNTER_OVERFLOW)) {			\
-			oprofile_add_sample(get_irq_regs(), n);		\
-			w_c0_perfcntr ## n(reg.counter[n]);		\
-			handled = IRQ_HANDLED;				\
-		}
-	HANDLE_COUNTER(3)
-	HANDLE_COUNTER(2)
-	HANDLE_COUNTER(1)
-	HANDLE_COUNTER(0)
-	}
-
-	return handled;
-}
-
-static int (*save_perf_irq)(void);
-
-static int __init mipsxx_init(void)
-{
-	int counters;
-
-	counters = n_counters();
-	if (counters == 0) {
-		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
-		return -ENODEV;
-	}
-
-#ifdef CONFIG_MIPS_MT_SMP
-	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
-	if (!cpu_has_mipsmt_pertccounters)
-		counters = counters_total_to_per_cpu(counters);
-#endif
-	on_each_cpu(reset_counters, (void *)(long)counters, 1);
-
-	op_model_mipsxx_ops.num_counters = counters;
-	switch (current_cpu_type()) {
-	case CPU_20KC:
-		op_model_mipsxx_ops.cpu_type = "mips/20K";
-		break;
-
-	case CPU_24K:
-		op_model_mipsxx_ops.cpu_type = "mips/24K";
-		break;
-
-	case CPU_25KF:
-		op_model_mipsxx_ops.cpu_type = "mips/25K";
-		break;
-
-	case CPU_1004K:
-#if 0
-		/* FIXME: report as 34K for now */
-		op_model_mipsxx_ops.cpu_type = "mips/1004K";
-		break;
-#endif
-
-	case CPU_34K:
-		op_model_mipsxx_ops.cpu_type = "mips/34K";
-		break;
-
-	case CPU_74K:
-		op_model_mipsxx_ops.cpu_type = "mips/74K";
-		break;
-
-	case CPU_5KC:
-		op_model_mipsxx_ops.cpu_type = "mips/5K";
-		break;
-
-	case CPU_R10000:
-		if ((current_cpu_data.processor_id & 0xff) == 0x20)
-			op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
-		else
-			op_model_mipsxx_ops.cpu_type = "mips/r10000";
-		break;
-
-	case CPU_R12000:
-	case CPU_R14000:
-		op_model_mipsxx_ops.cpu_type = "mips/r12000";
-		break;
-
-	case CPU_SB1:
-	case CPU_SB1A:
-		op_model_mipsxx_ops.cpu_type = "mips/sb1";
-		break;
-
-	default:
-		printk(KERN_ERR "Profiling unsupported for this CPU\n");
-
-		return -ENODEV;
-	}
-
-	save_perf_irq = perf_irq;
-	perf_irq = mipsxx_perfcount_handler;
-
-	return 0;
-}
-
-static void mipsxx_exit(void)
-{
-	int counters = op_model_mipsxx_ops.num_counters;
-
-	counters = counters_per_cpu_to_total(counters);
-	on_each_cpu(reset_counters, (void *)(long)counters, 1);
-
-	perf_irq = save_perf_irq;
-}
-
-struct op_mips_model op_model_mipsxx_ops = {
-	.reg_setup	= mipsxx_reg_setup,
-	.cpu_setup	= mipsxx_cpu_setup,
-	.init		= mipsxx_init,
-	.exit		= mipsxx_exit,
-	.cpu_start	= mipsxx_cpu_start,
-	.cpu_stop	= mipsxx_cpu_stop,
-};
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
deleted file mode 100644
index 48e7487..0000000
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/oprofile.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <asm/pmu.h>
-
-#include "op_impl.h"
-
-
-static struct rm9k_register_config {
-	unsigned int control;
-	unsigned int reset_counter1;
-	unsigned int reset_counter2;
-} reg;
-
-/* Compute all of the registers in preparation for enabling profiling.  */
-
-static void rm9000_reg_setup(struct op_counter_config *ctr)
-{
-	unsigned int control = 0;
-
-	/* Compute the performance counter control word.  */
-	/* For now count kernel and user mode */
-	if (ctr[0].enabled)
-		control |= RM9K_COUNTER1_EVENT(ctr[0].event) |
-		           RM9K_COUNTER1_KERNEL |
-		           RM9K_COUNTER1_USER |
-		           RM9K_COUNTER1_ENABLE;
-	if (ctr[1].enabled)
-		control |= RM9K_COUNTER2_EVENT(ctr[1].event) |
-		           RM9K_COUNTER2_KERNEL |
-		           RM9K_COUNTER2_USER |
-		           RM9K_COUNTER2_ENABLE;
-	reg.control = control;
-
-	reg.reset_counter1 = 0x80000000 - ctr[0].count;
-	reg.reset_counter2 = 0x80000000 - ctr[1].count;
-}
-
-/* Program all of the registers in preparation for enabling profiling.  */
-
-static void rm9000_cpu_setup(void *args)
-{
-	uint64_t perfcount;
-
-	perfcount = ((uint64_t) reg.reset_counter2 << 32) | reg.reset_counter1;
-	write_c0_perfcount(perfcount);
-}
-
-static void rm9000_cpu_start(void *args)
-{
-	/* Start all counters on current CPU */
-	write_c0_perfcontrol(reg.control);
-}
-
-static void rm9000_cpu_stop(void *args)
-{
-	/* Stop all counters on current CPU */
-	write_c0_perfcontrol(0);
-}
-
-static irqreturn_t rm9000_perfcount_handler(int irq, void *dev_id)
-{
-	unsigned int control = read_c0_perfcontrol();
-	struct pt_regs *regs = get_irq_regs();
-	uint32_t counter1, counter2;
-	uint64_t counters;
-
-	/*
-	 * RM9000 combines two 32-bit performance counters into a single
-	 * 64-bit coprocessor zero register.  To avoid a race updating the
-	 * registers we need to stop the counters while we're messing with
-	 * them ...
-	 */
-	write_c0_perfcontrol(0);
-
-	counters = read_c0_perfcount();
-	counter1 = counters;
-	counter2 = counters >> 32;
-
-	if (control & RM9K_COUNTER1_OVERFLOW) {
-		oprofile_add_sample(regs, 0);
-		counter1 = reg.reset_counter1;
-	}
-	if (control & RM9K_COUNTER2_OVERFLOW) {
-		oprofile_add_sample(regs, 1);
-		counter2 = reg.reset_counter2;
-	}
-
-	counters = ((uint64_t)counter2 << 32) | counter1;
-	write_c0_perfcount(counters);
-	write_c0_perfcontrol(reg.control);
-
-	return IRQ_HANDLED;
-}
-
-static int __init rm9000_init(void)
-{
-	return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
-	                   0, "Perfcounter", NULL);
-}
-
-static void rm9000_exit(void)
-{
-	free_irq(rm9000_perfcount_irq, NULL);
-}
-
-struct op_mips_model op_model_rm9000_ops = {
-	.reg_setup	= rm9000_reg_setup,
-	.cpu_setup	= rm9000_cpu_setup,
-	.init		= rm9000_init,
-	.exit		= rm9000_exit,
-	.cpu_start	= rm9000_cpu_start,
-	.cpu_stop	= rm9000_cpu_stop,
-	.cpu_type	= "mips/rm9000",
-	.num_counters	= 2
-};
-- 
1.6.3.3

Re: [PATCH v5 00/12] MIPS performance event support v5

[Deng-Cheng Zhu]

Hi, Ralf


According to the feedback received during the development of the previous
versions of Perf-events, changes to the code are getting slight. So I
think it's a good time to ask you to help review the code.

The patches 1~7 can be reviewed/applied/tested independently. And 8~12 are
trying to make Oprofile use Perf-events framework as backend, and are
depended on perf_event_rm9000.c and perf_event_loongson2.c to be added in.


Thanks for your time,

Deng-Cheng

Re: [PATCH v5 01/12] MIPS/Oprofile: extract PMU defines/helper functions for sharing

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
[...]
>
> diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
[...]
> +
> +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
> +    defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
> +

Why predicate the entire contents of the file?

In any event, if you keep it, it shold probably be something like:

     #if defined(CONFIG_CPU_MIPSR1) || defined(CONFIG_CPU_MIPSR2)


> +#define M_CONFIG1_PC	(1<<  4)
> +
> +#define M_PERFCTL_EXL			(1UL<<   0)
> +#define M_PERFCTL_KERNEL		(1UL<<   1)
> +#define M_PERFCTL_SUPERVISOR		(1UL<<   2)
> +#define M_PERFCTL_USER			(1UL<<   3)
> +#define M_PERFCTL_INTERRUPT_ENABLE	(1UL<<   4)
> +#define M_PERFCTL_EVENT(event)		(((event)&  0x3ff)<<  5)
> +#define M_PERFCTL_VPEID(vpe)		((vpe)<<  16)
> +#define M_PERFCTL_MT_EN(filter)		((filter)<<  20)
> +#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
> +#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
> +#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
> +#define M_PERFCTL_TCID(tcid)		((tcid)<<  22)
> +#define M_PERFCTL_WIDE			(1UL<<  30)
> +#define M_PERFCTL_MORE			(1UL<<  31)
> +
> +#define M_COUNTER_OVERFLOW		(1UL<<  31)
> +

Some or all of that should probably go in asm/mipsregs.h


[...]
> +
> +#define __define_perf_accessors(r, n, np)				\
> +									\
> +static inline unsigned int r_c0_ ## r ## n(void)			\
> +{									\
> +	unsigned int cpu = vpe_id();					\
> +									\
> +	switch (cpu) {							\
> +	case 0:								\
> +		return read_c0_ ## r ## n();				\
> +	case 1:								\
> +		return read_c0_ ## r ## np();				\
> +	default:							\

Are 0 and 1 really the only conceivable values?


David Daney

Re: [PATCH v5 02/12] MIPS: use generic atomic64 in non-64bit kernels

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> 64bit kernel has already had its atomic64 functions. Except for that, we
> use the generic spinlocked version. The atomic64 types and related
> functions are needed for the Linux performance counter subsystem.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>

Acked-by: David Daney <ddaney@caviumnetworks.com>

> ---
>   arch/mips/Kconfig              |    1 +
>   arch/mips/include/asm/atomic.h |    4 ++++
>   2 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index cdaae94..ef3d8ca 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -4,6 +4,7 @@ config MIPS
>   	select HAVE_GENERIC_DMA_COHERENT
>   	select HAVE_IDE
>   	select HAVE_OPROFILE
> +	select GENERIC_ATOMIC64 if !64BIT
>   	select HAVE_ARCH_KGDB
>   	select HAVE_FUNCTION_TRACER
>   	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
> diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
> index 59dc0c7..23990cb 100644
> --- a/arch/mips/include/asm/atomic.h
> +++ b/arch/mips/include/asm/atomic.h
> @@ -782,6 +782,10 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
>    */
>   #define atomic64_add_negative(i, v) (atomic64_add_return(i, (v))<  0)
>
> +#else /* ! CONFIG_64BIT */
> +
> +#include<asm-generic/atomic64.h>
> +
>   #endif /* CONFIG_64BIT */
>
>   /*

Re: [PATCH v5 03/12] MIPS: add support for software performance events

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> Software events are required as part of the measurable stuff by the
> Linux performance counter subsystem. Here is the list of events added by
> this patch:
> PERF_COUNT_SW_PAGE_FAULTS
> PERF_COUNT_SW_PAGE_FAULTS_MIN
> PERF_COUNT_SW_PAGE_FAULTS_MAJ
> PERF_COUNT_SW_ALIGNMENT_FAULTS
> PERF_COUNT_SW_EMULATION_FAULTS
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>

Acked-by: David Daney <ddaney@caviumnetworks.com>

> ---
>   arch/mips/Kconfig            |    2 ++
>   arch/mips/kernel/traps.c     |   18 +++++++++++++++---
>   arch/mips/kernel/unaligned.c |    5 +++++
>   arch/mips/math-emu/cp1emu.c  |    3 +++
>   arch/mips/mm/fault.c         |   11 +++++++++--
>   5 files changed, 34 insertions(+), 5 deletions(-)
>
[...]

Re: [PATCH v5 04/12] MIPS: add support for hardware performance events (skeleton)

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> This patch provides the skeleton of the HW perf event support. To enable
> this feature, we can not choose the SMTC kernel; Oprofile should be
> disabled; kernel performance events be selected. Then we can enable it in
> Kernel type menu.
>
> Oprofile for MIPS platforms initializes irq at arch init time. Currently
> we do not change this logic to allow PMU reservation.
>
> If a platform has EIC, we can use the irq base and perf counter irq
> offset defines for the interrupt controller in mipspmu_get_irq().
>
> Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely,
> mipsxx/loongson2/rm9000, can be supported by adding corresponding lower
> level C files at the bottom. The suggested names of these files are
> perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for
> example, we can do this by adding "#include perf_event_mipsxx.c" at the
> bottom of perf_event.c.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/Kconfig                  |    8 +
>   arch/mips/include/asm/perf_event.h |   28 ++
>   arch/mips/kernel/Makefile          |    2 +
>   arch/mips/kernel/perf_event.c      |  503 ++++++++++++++++++++++++++++++++++++
>   4 files changed, 541 insertions(+), 0 deletions(-)
>   create mode 100644 arch/mips/include/asm/perf_event.h
>   create mode 100644 arch/mips/kernel/perf_event.c
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 1bccfe5..27577b4 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -1888,6 +1888,14 @@ config NODES_SHIFT
>   	default "6"
>   	depends on NEED_MULTIPLE_NODES
>
> +config HW_PERF_EVENTS
> +	bool "Enable hardware performance counter support for perf events"
> +	depends on PERF_EVENTS&&  !MIPS_MT_SMTC&&  OPROFILE=n&&  CPU_MIPS32


This depends on not consistent with the #if conditions in [01/12] for 
pmu.h.  They should be I think.

Probably removing the tests from pmu.h and encoding them here is better.


> +	default y
> +	help
> +	  Enable hardware performance counter support for perf events. If
> +	  disabled, perf events will use software events only.
> +
>   source "mm/Kconfig"
>
>   config SMP
> diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h
> new file mode 100644
> index 0000000..bcf54bc
> --- /dev/null
> +++ b/arch/mips/include/asm/perf_event.h
> @@ -0,0 +1,28 @@
> +/*
> + * linux/arch/mips/include/asm/perf_event.h
> + *
> + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu

IANAL, but who holds the copyright?  You or MTI ?



> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __MIPS_PERF_EVENT_H__
> +#define __MIPS_PERF_EVENT_H__
> +
> +extern int (*perf_irq)(void);
> +

This shadows the declaration in asm/time.h.  Declare it in exactly one 
place please.


[...]
> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
> new file mode 100644
> index 0000000..788815f
> --- /dev/null
> +++ b/arch/mips/kernel/perf_event.c
> @@ -0,0 +1,503 @@
> +/*
> + * Linux performance counter support for MIPS.
> + *
> + * Copyright (C) 2010 MIPS Technologies, Inc. Deng-Cheng Zhu
> + *

Same thing about the copyright.


> + * This code is based on the implementation for ARM, which is in turn
> + * based on the sparc64 perf event code and the x86 code. Performance
> + * counter access is based on the MIPS Oprofile code.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<linux/cpumask.h>
> +#include<linux/interrupt.h>
> +#include<linux/smp.h>
> +#include<linux/kernel.h>
> +#include<linux/perf_event.h>
> +#include<linux/uaccess.h>
> +
> +#include<asm/irq.h>
> +#include<asm/irq_regs.h>
> +#include<asm/stacktrace.h>
> +#include<asm/pmu.h>
> +
> +
> +#define MAX_PERIOD ((1ULL<<  32) - 1)
> +
> +struct cpu_hw_events {
> +	/* Array of events on this cpu. */
> +	struct perf_event	*events[MIPS_MAX_HWEVENTS];
> +
> +	/*
> +	 * Set the bit (indexed by the counter number) when the counter
> +	 * is used for an event.
> +	 */
> +	unsigned long		used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
> +
> +	/*
> +	 * The borrowed MSB for the performance counter. A MIPS performance
> +	 * counter uses its bit 31 as a factor of determining whether a counter

Not quite true.  They use the high bit, that can be either 31 or 63 
depending on the width of the counters.


[...]
> +
> +struct mips_pmu {
> +	const char	*name;
> +	irqreturn_t	(*handle_irq)(int irq, void *dev);
> +	int		(*handle_shared_irq)(void);
> +	void		(*start)(void);
> +	void		(*stop)(void);
> +	int		(*alloc_counter)(struct cpu_hw_events *cpuc,
> +					struct hw_perf_event *hwc);
> +	unsigned int	(*read_counter)(unsigned int idx);
> +	void		(*write_counter)(unsigned int idx, unsigned int val);

Counters can be 64-bits wide, unsigned int is only 32-bits wide.


[...]

David Daney

Re: [PATCH v5 05/12] MIPS/Perf-events: add callchain support

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> This patch adds callchain support for MIPS Perf-events. For more info on
> this feature, please refer to tools/perf/Documentation/perf-report.txt
> and tools/perf/design.txt.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>

Acked-by: David Daney <ddaney@caviumnetworks.com>

> ---
>   arch/mips/kernel/perf_event.c |   98 ++++++++++++++++++++++++++++++++++++++++-
>   1 files changed, 97 insertions(+), 1 deletions(-)
>
[...]

Re: [PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx)

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> This patch adds the mipsxx Perf-event support based on the skeleton.
> Generic hardware events and cache events are now fully implemented for
> the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as
> R10000/SB1), the generic hardware event tables and cache event tables
> need to be filled out. To support other CPUs which have different PMU
> than mipsxx, such as RM9000 and LOONGSON2, the additional files
> perf_event_$cpu.c need to be created.
>
> To test the functionality of Perf-event, you may want to compile the tool
> "perf" for your MIPS platform. You can refer to the following URL:
> http://www.linux-mips.org/archives/linux-mips/2010-04/msg00158.html
>
> Please note: Before that patch is accepted, you can choose a "specific"
> rmb() which is suitable for your platform -- an example is provided in
> the description of that patch.
>
> You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile
> for your libs, includes, etc.
>
> In case you encounter the boot failure in SMVP kernel on multi-threading
> CPUs, you may take a look at:
> http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/kernel/perf_event.c        |    2 +
>   arch/mips/kernel/perf_event_mipsxx.c |  719 ++++++++++++++++++++++++++++++++++
>   2 files changed, 721 insertions(+), 0 deletions(-)
>   create mode 100644 arch/mips/kernel/perf_event_mipsxx.c
>

General comments:

Can you separate the code that reads and writes the performance counter 
registers from the definitions of the various counters themselves?

Also take into account that the counter registers may be either 32 or 64 
bits wide.  The interfaces you are defining should take that into 
account even if the specific implementations only work with 32-bit 
registers.

Thanks,
David Daney

Re: [PATCH v5 07/12] MIPS/Perf-events: add raw event support for mipsxx 24K/34K/74K/1004K

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> Raw event is an important part of Perf-events. It helps the user collect
> performance data for events that are not listed as the generic hardware
> events and cache events but ARE supported by the CPU's PMU.
>
> This patch adds this feature for mipsxx 24K/34K/74K/1004K. For how to use
> it, please refer to processor core software user's manual and the
> comments for mipsxx_pmu_map_raw_event() for more details.
>
> Please note that this is a "precise" implementation, which means the
> kernel will check whether the requested raw events are supported by this
> CPU and which hardware counters can be assigned for them.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/kernel/perf_event.c        |    4 +
>   arch/mips/kernel/perf_event_mipsxx.c |  152 +++++++++++++++++++++++++++++++++-
>   2 files changed, 155 insertions(+), 1 deletions(-)
>

Should this just be folded into the other patches?

I would also reiterate that perhaps the generic support functions be 
separated from the processor specific event definitions.

David Daney

Re: [PATCH v5 08/12] MIPS: move mipsxx pmu helper functions to Perf-events

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> This is the 1st patch starting to use Perf-events as the backend of
> Oprofile. Here we move pmu helper functions and macros between pmu.h and
> perf_event*.c for mipsxx.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/include/asm/pmu.h          |  160 ++--------------------------------
>   arch/mips/kernel/perf_event.c        |    2 +
>   arch/mips/kernel/perf_event_mipsxx.c |  145 +++++++++++++++++++++++++++++--
>   3 files changed, 147 insertions(+), 160 deletions(-)
>

Is is possible to fold this patch also?  I don't think we need to follow 
the exact evolution of the new files.

David Daney

Re: [PATCH v5 09/12] MIPS/Perf-events: replace pmu names with numeric IDs

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> Using Perf-events as the backend, clients such as Oprofile will need to
> enquire the pmu names. A convenient way to do this is to use pmu id to
> index the exported name array. And this is what we are doing here.
>
> NOTE: While using scripts/checkpatch.pl to check this patch, a style
> warning is reported. I suppose it is a false positive, and will report to
> the maintainer. The message is:
> =======================================
> WARNING:
> EXPORT_SYMBOL(foo); should immediately follow its function/variable
> #81: FILE: arch/mips/kernel/perf_event.c:112:
> +EXPORT_SYMBOL_GPL(mips_pmu_names);
> =======================================

I don't like this one.

In cpu-probe.c we used to have this same type of parallel name array, 
and it was messy.

You know what type of cpu you are running on, so I don't understand the 
advantage of querying by name.  What possible use could there be to 
knowing the names of processors that are not applicable to the current 
runtime?

David Daney



>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/include/asm/pmu.h          |   26 ++++++++++++++++++++++++++
>   arch/mips/kernel/perf_event.c        |   31 ++++++++++++++++++++++++++++++-
>   arch/mips/kernel/perf_event_mipsxx.c |   12 +++++++-----
>   3 files changed, 63 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
> index 2822810..16d4fcd 100644
> --- a/arch/mips/include/asm/pmu.h
> +++ b/arch/mips/include/asm/pmu.h
> @@ -89,4 +89,30 @@ extern unsigned int rm9000_perfcount_irq;
>
>   #endif /* CONFIG_CPU_* */
>
> +/* MIPS PMU IDs for use by internal perf clients. */
> +enum mips_pmu_id {
> +	/* mipsxx */
> +	MIPS_PMU_ID_20K = 0,
> +	MIPS_PMU_ID_24K,
> +	MIPS_PMU_ID_25K,
> +	MIPS_PMU_ID_1004K,
> +	MIPS_PMU_ID_34K,
> +	MIPS_PMU_ID_74K,
> +	MIPS_PMU_ID_5K,
> +	MIPS_PMU_ID_R10000V2,
> +	MIPS_PMU_ID_R10000,
> +	MIPS_PMU_ID_R12000,
> +	MIPS_PMU_ID_SB1,
> +	/* rm9000 */
> +	MIPS_PMU_ID_RM9000,
> +	/* loongson2 */
> +	MIPS_PMU_ID_LOONGSON2,
> +	/* unsupported */
> +	MIPS_PMU_ID_UNSUPPORTED,
> +};
> +
> +extern const char *mips_pmu_names[];
> +
> +extern enum mips_pmu_id mipspmu_get_pmu_id(void);
> +
>   #endif /* __MIPS_PMU_H__ */
> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
> index 0ef54e6..f05e2b1 100644
> --- a/arch/mips/kernel/perf_event.c
> +++ b/arch/mips/kernel/perf_event.c
> @@ -88,8 +88,31 @@ static DEFINE_MUTEX(raw_event_mutex);
>   #define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
>   #define C(x) PERF_COUNT_HW_CACHE_##x
>
> +/* MIPS PMU names */
> +const char *mips_pmu_names[] = {
> +	/* mipsxx */
> +	[MIPS_PMU_ID_20K]		= "mips/20K",
> +	[MIPS_PMU_ID_24K]		= "mips/24K",
> +	[MIPS_PMU_ID_25K]		= "mips/25K",
> +	[MIPS_PMU_ID_1004K]		= "mips/1004K",
> +	[MIPS_PMU_ID_34K]		= "mips/34K",
> +	[MIPS_PMU_ID_74K]		= "mips/74K",
> +	[MIPS_PMU_ID_5K]		= "mips/5K",
> +	[MIPS_PMU_ID_R10000V2]		= "mips/r10000-v2.x",
> +	[MIPS_PMU_ID_R10000]		= "mips/r10000",
> +	[MIPS_PMU_ID_R12000]		= "mips/r12000",
> +	[MIPS_PMU_ID_SB1]		= "mips/sb1",
> +	/* rm9000 */
> +	[MIPS_PMU_ID_RM9000]		= "mips/rm9000",
> +	/* loongson2 */
> +	[MIPS_PMU_ID_LOONGSON2]		= "mips/loongson2",
> +	/* unsupported */
> +	[MIPS_PMU_ID_UNSUPPORTED]	= NULL,
> +};
> +EXPORT_SYMBOL_GPL(mips_pmu_names);
> +
>   struct mips_pmu {
> -	const char	*name;
> +	enum mips_pmu_id id;
>   	irqreturn_t	(*handle_irq)(int irq, void *dev);
>   	int		(*handle_shared_irq)(void);
>   	void		(*start)(void);
> @@ -111,6 +134,12 @@ struct mips_pmu {
>
>   static const struct mips_pmu *mipspmu;
>
> +enum mips_pmu_id mipspmu_get_pmu_id(void)
> +{
> +	return mipspmu ? mipspmu->id : MIPS_PMU_ID_UNSUPPORTED;
> +}
> +EXPORT_SYMBOL_GPL(mipspmu_get_pmu_id);
> +
>   static int
>   mipspmu_event_set_period(struct perf_event *event,
>   			struct hw_perf_event *hwc,
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> index 1c92917..4e37a3a 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -962,22 +962,22 @@ init_hw_perf_events(void)
>
>   	switch (current_cpu_type()) {
>   	case CPU_24K:
> -		mipsxxcore_pmu.name = "mips/24K";
> +		mipsxxcore_pmu.id = MIPS_PMU_ID_24K;
>   		mipsxxcore_pmu.num_counters = counters;
>   		mipspmu =&mipsxxcore_pmu;
>   		break;
>   	case CPU_34K:
> -		mipsxxcore_pmu.name = "mips/34K";
> +		mipsxxcore_pmu.id = MIPS_PMU_ID_34K;
>   		mipsxxcore_pmu.num_counters = counters;
>   		mipspmu =&mipsxxcore_pmu;
>   		break;
>   	case CPU_74K:
> -		mipsxx74Kcore_pmu.name = "mips/74K";
> +		mipsxx74Kcore_pmu.id = MIPS_PMU_ID_74K;
>   		mipsxx74Kcore_pmu.num_counters = counters;
>   		mipspmu =&mipsxx74Kcore_pmu;
>   		break;
>   	case CPU_1004K:
> -		mipsxxcore_pmu.name = "mips/1004K";
> +		mipsxxcore_pmu.id = MIPS_PMU_ID_1004K;
>   		mipsxxcore_pmu.num_counters = counters;
>   		mipspmu =&mipsxxcore_pmu;
>   		break;
> @@ -989,7 +989,9 @@ init_hw_perf_events(void)
>
>   	if (mipspmu)
>   		pr_cont("%s PMU enabled, %d counters available to each "
> -			"CPU\n", mipspmu->name, mipspmu->num_counters);
> +			"CPU\n",
> +			mips_pmu_names[mipspmu->id],
> +			mipspmu->num_counters);
>
>   	return 0;
>   }

Re: [PATCH v5 10/12] MIPS/Perf-events: allow modules to get pmu number of counters

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> Oprofile module needs a function to get the number of pmu counters in its
> high level interfaces.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/include/asm/pmu.h   |    1 +
>   arch/mips/kernel/perf_event.c |    6 ++++++
>   2 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/include/asm/pmu.h b/arch/mips/include/asm/pmu.h
> index 16d4fcd..023a915 100644
> --- a/arch/mips/include/asm/pmu.h
> +++ b/arch/mips/include/asm/pmu.h
> @@ -114,5 +114,6 @@ enum mips_pmu_id {
>   extern const char *mips_pmu_names[];
>
>   extern enum mips_pmu_id mipspmu_get_pmu_id(void);
> +extern int mipspmu_get_max_events(void);
>
>   #endif /* __MIPS_PMU_H__ */
> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
> index f05e2b1..dc3a553 100644
> --- a/arch/mips/kernel/perf_event.c
> +++ b/arch/mips/kernel/perf_event.c
> @@ -140,6 +140,12 @@ enum mips_pmu_id mipspmu_get_pmu_id(void)
>   }
>   EXPORT_SYMBOL_GPL(mipspmu_get_pmu_id);
>
> +int mipspmu_get_max_events(void)
> +{
> +	return mipspmu ? mipspmu->num_counters : 0;
> +}
> +EXPORT_SYMBOL_GPL(mipspmu_get_max_events);
> +

Why is it called 'max_events' when it is returning the number of 
counters?  How about mipspmu_get_max_counters?

Do we even need this accessor?

Why not just query it from the struct mips_pmu?  Don't you need the 
mipspmu structure anyhow to be able to use the counters?

David Daney

Re: [PATCH v5 11/12] MIPS/Oprofile: use Perf-events framework as backend

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> This patch is based on Will Deacon's work for ARM. The well-written
> reasons and ideas can be found here:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-April/013210.html
>
> This effort makes the bug-fixes shared by different pmu users/clients
> (for now, Oprofile&  Perf-events), and make them coexist in the system
> without lock issues, and make their results comparable.
>
> So this patch moves Oprofile on top of Perf-events by replacing its
> original interfaces with new ones calling Perf-events.
>
> Oprofile uses raw events, so Perf-events (mipsxx in this patch) is
> modified to support more mipsxx CPUs.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/kernel/perf_event.c        |    7 +-
>   arch/mips/kernel/perf_event_mipsxx.c |  125 ++++++++++++------
>   arch/mips/oprofile/common.c          |  237 +++++++++++++++++++++++++---------
>   3 files changed, 266 insertions(+), 103 deletions(-)
>
[...]
>
>   static int __init
> @@ -963,35 +960,77 @@ init_hw_perf_events(void)
>   	switch (current_cpu_type()) {
>   	case CPU_24K:
>   		mipsxxcore_pmu.id = MIPS_PMU_ID_24K;
> -		mipsxxcore_pmu.num_counters = counters;
> -		mipspmu =&mipsxxcore_pmu;
> +		mipsxxcore_pmu.general_event_map =&mipsxxcore_event_map;
> +		mipsxxcore_pmu.cache_event_map =&mipsxxcore_cache_map;
>   		break;
>   	case CPU_34K:
>   		mipsxxcore_pmu.id = MIPS_PMU_ID_34K;
> -		mipsxxcore_pmu.num_counters = counters;
> -		mipspmu =&mipsxxcore_pmu;
> +		mipsxxcore_pmu.general_event_map =&mipsxxcore_event_map;
> +		mipsxxcore_pmu.cache_event_map =&mipsxxcore_cache_map;
>   		break;

The mips perf events system should already know what type of cpu it is 
running on.

Can we have all this processor specific perf/counter stuff live in one 
place and simplify all of this?


[...]

> +/*
> + * Attributes are created as "pinned" events and so are permanently
> + * scheduled on the PMU.
> + */
> +static void op_perf_setup(void)
> +{
> +	int i;
> +	u32 size = sizeof(struct perf_event_attr);
> +	struct perf_event_attr *attr;
> +
> +	for (i = 0; i<  perf_num_counters; ++i) {
> +		attr =&ctr[i].attr;
> +		memset(attr, 0, size);
> +		attr->type		= PERF_TYPE_RAW;
> +		attr->size		= size;
> +		attr->config		= ctr[i].event + (i&  0x1 ? 128 : 0);

Too many magic numbers.  Lets have symbolic names.

[...]

Thanks,
David Daney

Re: [PATCH v5 12/12] MIPS/Oprofile: remove old files and update Kconfig/Makefile

[David Daney]

On 05/27/2010 06:03 AM, Deng-Cheng Zhu wrote:
> Now that Oprofile uses Perf-events as backend, its old framework files
> are not needed. Kconfig is modified to let hardware performance events be
> the prerequisite of Oprofile.
>
> Signed-off-by: Deng-Cheng Zhu<dengcheng.zhu@gmail.com>
> ---
>   arch/mips/Kconfig                       |    4 +-
>   arch/mips/oprofile/Makefile             |    7 -
>   arch/mips/oprofile/op_impl.h            |   39 -----
>   arch/mips/oprofile/op_model_loongson2.c |  139 ------------------
>   arch/mips/oprofile/op_model_mipsxx.c    |  237 -------------------------------
>   arch/mips/oprofile/op_model_rm9000.c    |  124 ----------------
>   6 files changed, 2 insertions(+), 548 deletions(-)
>   delete mode 100644 arch/mips/oprofile/op_impl.h
>   delete mode 100644 arch/mips/oprofile/op_model_loongson2.c
>   delete mode 100644 arch/mips/oprofile/op_model_mipsxx.c
>   delete mode 100644 arch/mips/oprofile/op_model_rm9000.c
>


This patch could be folded into the previous one.

If the previous patch really makes these unused, it shouldn't leave them 
hanging around.


David Daney

Re: [PATCH v5 01/12] MIPS/Oprofile: extract PMU defines/helper functions for sharing

[Deng-Cheng Zhu]

Hi, David


Thanks for your comments! I'm replying to you in the patch order. If my
comments are wrong or are bad ideas, please point out.


2010/5/28 David Daney <david.s.daney@gmail.com>:
> Why predicate the entire contents of the file?
>
> In any event, if you keep it, it shold probably be something like:
>
>    #if defined(CONFIG_CPU_MIPSR1) || defined(CONFIG_CPU_MIPSR2)
[DC]:
1) This line is not for the "entire" contents of the file, other CPUs
LOONGSON2 and RM9000 are here.
2) The CONFIG_CPU* came from the Makefile of oprofile. If other CPUs are
newly supported, we can add into the #if #elif.
3) The perf counter helper functions are special to mipsxx/loongson2/rm9000
espcially the reset_counter() will be implemented respectively. Although
they will be moved to perf_event_$cpu.c when Oprofile uses Perf-events as
backend, they are currently shared by Oprofile and Perf-events to reduce
code copying.


> Some or all of that should probably go in asm/mipsregs.h
[DC]: Now that we create pmu.h and these #define's are originally in
op_model_$cpu.c not in mipsregs.h, how about keeping them here? BTW, after
making Oprofile use Perf-events as backend (patches 8~12 do this), pmu.h
will only contain register definitions (no static function definitions),
then we can consider deleting pmu.h and moving its contents to mipsregs.h,
is it OK?


> Are 0 and 1 really the only conceivable values?
[DC]: This is also from Oprofile. If we use:
#define vpe_id()       (cpu_has_mipsmt_pertccounters ? \
                       0 : cpu_data[smp_processor_id()].vpe_id)
The possible return value is supposed to be 0 or 1.


Deng-Cheng

Re: [PATCH v5 01/12] MIPS/Oprofile: extract PMU defines/helper functions for sharing

[Deng-Cheng Zhu]

Hi, David


Thanks for your comments! I'm replying to you in the patch order. If my
comments are wrong or are bad ideas, please point out.


2010/5/28 David Daney <david.s.daney@gmail.com>:
> Why predicate the entire contents of the file?
>
> In any event, if you keep it, it shold probably be something like:
>
>    #if defined(CONFIG_CPU_MIPSR1) || defined(CONFIG_CPU_MIPSR2)
[DC]:
1) This line is not for the "entire" contents of the file, other CPUs
LOONGSON2 and RM9000 are here.
2) The CONFIG_CPU* came from the Makefile of oprofile. If other CPUs are
newly supported, we can add into the #if #elif.
3) The perf counter helper functions are special to mipsxx/loongson2/rm9000
espcially the reset_counter() will be implemented respectively. Although
they will be moved to perf_event_$cpu.c when Oprofile uses Perf-events as
backend, they are currently shared by Oprofile and Perf-events to reduce
code copying.


> Some or all of that should probably go in asm/mipsregs.h
[DC]: Now that we create pmu.h and these #define's are originally in
op_model_$cpu.c not in mipsregs.h, how about keeping them here? BTW, after
making Oprofile use Perf-events as backend (patches 8~12 do this), pmu.h
will only contain register definitions (no static function definitions),
then we can consider deleting pmu.h and moving its contents to mipsregs.h,
is it OK?


> Are 0 and 1 really the only conceivable values?
[DC]: This is also from Oprofile. If we use:
#define vpe_id()       (cpu_has_mipsmt_pertccounters ? \
                       0 : cpu_data[smp_processor_id()].vpe_id)
The possible return value is supposed to be 0 or 1.


Deng-Cheng

Re: [PATCH v5 04/12] MIPS: add support for hardware performance events (skeleton)

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> This depends on not consistent with the #if conditions in [01/12] for pmu.h.
>  They should be I think.
[DC]: It's a subset. If the code passes the test on other CPUs (such as
CPU_SB1), we can add them here.


> Probably removing the tests from pmu.h and encoding them here is better.
[DC]: According to my comments for [1/12], how about keeping them untouched
for now?


> IANAL, but who holds the copyright?  You or MTI ?
[DC]: OK. Will change like this:
Copyright (C) 2010 MIPS Technologies, Inc.
Author: Deng-Cheng Zhu


> This shadows the declaration in asm/time.h.  Declare it in exactly one place
> please.
[DC]: OK.


> Same thing about the copyright.
[DC]: OK.


> Not quite true.  They use the high bit, that can be either 31 or 63
> depending on the width of the counters.
[DC]: OK. Will change to consider 64-bit counters.


> Counters can be 64-bits wide, unsigned int is only 32-bits wide.
[DC]: OK.


Deng-Cheng

Re: [PATCH v5 04/12] MIPS: add support for hardware performance events (skeleton)

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> This depends on not consistent with the #if conditions in [01/12] for pmu.h.
>  They should be I think.
[DC]: It's a subset. If the code passes the test on other CPUs (such as
CPU_SB1), we can add them here.


> Probably removing the tests from pmu.h and encoding them here is better.
[DC]: According to my comments for [1/12], how about keeping them untouched
for now?


> IANAL, but who holds the copyright?  You or MTI ?
[DC]: OK. Will change like this:
Copyright (C) 2010 MIPS Technologies, Inc.
Author: Deng-Cheng Zhu


> This shadows the declaration in asm/time.h.  Declare it in exactly one place
> please.
[DC]: OK.


> Same thing about the copyright.
[DC]: OK.


> Not quite true.  They use the high bit, that can be either 31 or 63
> depending on the width of the counters.
[DC]: OK. Will change to consider 64-bit counters.


> Counters can be 64-bits wide, unsigned int is only 32-bits wide.
[DC]: OK.


Deng-Cheng

Re: [PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx)

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> General comments:
>
> Can you separate the code that reads and writes the performance counter
> registers from the definitions of the various counters themselves?
[DC]:
1) Do you mean to move M_PERFCTL_* stuff out into pmu.h (or mipsregs.h)?
If yes, that's OK. Again (my reply for [1/12] mentions this for the 1st
time): After making Oprofile use Perf-events as backend (patches 8~12 do
this), register definitions and read/write functions will locate in pmu.h
(or mipsregs.h) and perf_event_$cpu.c, respectively.
2) According to your reply to [7/12], do you mean the perf counter
read/write functions (such as mipsxx_pmu_read_counter()) are generic
support functions? No, they are specific for mipsxx CPUs.


> Also take into account that the counter registers may be either 32 or 64
> bits wide.  The interfaces you are defining should take that into account
> even if the specific implementations only work with 32-bit registers.
[DC]: OK.


Deng-Cheng

Re: [PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx)

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> General comments:
>
> Can you separate the code that reads and writes the performance counter
> registers from the definitions of the various counters themselves?
[DC]:
1) Do you mean to move M_PERFCTL_* stuff out into pmu.h (or mipsregs.h)?
If yes, that's OK. Again (my reply for [1/12] mentions this for the 1st
time): After making Oprofile use Perf-events as backend (patches 8~12 do
this), register definitions and read/write functions will locate in pmu.h
(or mipsregs.h) and perf_event_$cpu.c, respectively.
2) According to your reply to [7/12], do you mean the perf counter
read/write functions (such as mipsxx_pmu_read_counter()) are generic
support functions? No, they are specific for mipsxx CPUs.


> Also take into account that the counter registers may be either 32 or 64
> bits wide.  The interfaces you are defining should take that into account
> even if the specific implementations only work with 32-bit registers.
[DC]: OK.


Deng-Cheng

Re: [PATCH v5 07/12] MIPS/Perf-events: add raw event support for mipsxx 24K/34K/74K/1004K

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> Should this just be folded into the other patches?
[DC]: OK.


> I would also reiterate that perhaps the generic support functions be
> separated from the processor specific event definitions.
[DC]: Which generic support functions in perf_event_mipsxx.c? Please refer
to my reply for [6/12].


Deng-Cheng

Re: [PATCH v5 07/12] MIPS/Perf-events: add raw event support for mipsxx 24K/34K/74K/1004K

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> Should this just be folded into the other patches?
[DC]: OK.


> I would also reiterate that perhaps the generic support functions be
> separated from the processor specific event definitions.
[DC]: Which generic support functions in perf_event_mipsxx.c? Please refer
to my reply for [6/12].


Deng-Cheng

Re: [PATCH v5 08/12] MIPS: move mipsxx pmu helper functions to Perf-events

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> Is is possible to fold this patch also?  I don't think we need to follow the
> exact evolution of the new files.
[DC]: Patches 1~7 are the primary implementation for MIPS Perf-events. And
patches 8~12 make Oprofile use Perf-events as backend. By doing this, 1~7
can be reviewed/applied/built/tested independently. Maybe you are referring
to Patchwork, so the [00/12] is not visible, here is the link:
http://www.linux-mips.org/archives/linux-mips/2010-05/msg00326.html


Deng-Cheng

Re: [PATCH v5 08/12] MIPS: move mipsxx pmu helper functions to Perf-events

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> Is is possible to fold this patch also?  I don't think we need to follow the
> exact evolution of the new files.
[DC]: Patches 1~7 are the primary implementation for MIPS Perf-events. And
patches 8~12 make Oprofile use Perf-events as backend. By doing this, 1~7
can be reviewed/applied/built/tested independently. Maybe you are referring
to Patchwork, so the [00/12] is not visible, here is the link:
http://www.linux-mips.org/archives/linux-mips/2010-05/msg00326.html


Deng-Cheng

Re: [PATCH v5 09/12] MIPS/Perf-events: replace pmu names with numeric IDs

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> I don't like this one.
>
> In cpu-probe.c we used to have this same type of parallel name array, and it
> was messy.
>
> You know what type of cpu you are running on, so I don't understand the
> advantage of querying by name.  What possible use could there be to knowing
> the names of processors that are not applicable to the current runtime?
[DC]:
1) It's not "querying by name", but "querying name by enum numbers".
2) Oprofile (now a client of Perf-events) needs to print out the PMU names
to the user. If we don't want this patch, we have 2 methods to do this:
- Export the whole mipspmu, and use mipspmu->name;
- Like the old Oprofile (mipsxx), do a 2nd "switch(current_cpu_type())",
the 1st is in perf_event_mipsxx.c init_hw_perf_events().
3) Exporting a single name array indexed by enum IDs should be convenient
for maintaince. Maybe I'm missing some considerations... But how do we
allow Oprofile to get the string name to the user? Not even need to do it?


Deng-Cheng

Re: [PATCH v5 09/12] MIPS/Perf-events: replace pmu names with numeric IDs

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> I don't like this one.
>
> In cpu-probe.c we used to have this same type of parallel name array, and it
> was messy.
>
> You know what type of cpu you are running on, so I don't understand the
> advantage of querying by name.  What possible use could there be to knowing
> the names of processors that are not applicable to the current runtime?
[DC]:
1) It's not "querying by name", but "querying name by enum numbers".
2) Oprofile (now a client of Perf-events) needs to print out the PMU names
to the user. If we don't want this patch, we have 2 methods to do this:
- Export the whole mipspmu, and use mipspmu->name;
- Like the old Oprofile (mipsxx), do a 2nd "switch(current_cpu_type())",
the 1st is in perf_event_mipsxx.c init_hw_perf_events().
3) Exporting a single name array indexed by enum IDs should be convenient
for maintaince. Maybe I'm missing some considerations... But how do we
allow Oprofile to get the string name to the user? Not even need to do it?


Deng-Cheng

Re: [PATCH v5 10/12] MIPS/Perf-events: allow modules to get pmu number of counters

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> Why is it called 'max_events' when it is returning the number of counters?
>  How about mipspmu_get_max_counters?
[DC]: OK.


> Do we even need this accessor?
>
> Why not just query it from the struct mips_pmu?  Don't you need the mipspmu
> structure anyhow to be able to use the counters?
[DC]: This is for the code outside of Perf-events, such as the module of
the new Oprofile which is a client of Perf-events. If we don't need this,
we have to export the whole mipspmu.


Deng-Cheng

Re: [PATCH v5 10/12] MIPS/Perf-events: allow modules to get pmu number of counters

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> Why is it called 'max_events' when it is returning the number of counters?
>  How about mipspmu_get_max_counters?
[DC]: OK.


> Do we even need this accessor?
>
> Why not just query it from the struct mips_pmu?  Don't you need the mipspmu
> structure anyhow to be able to use the counters?
[DC]: This is for the code outside of Perf-events, such as the module of
the new Oprofile which is a client of Perf-events. If we don't need this,
we have to export the whole mipspmu.


Deng-Cheng

Re: [PATCH v5 11/12] MIPS/Oprofile: use Perf-events framework as backend

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> The mips perf events system should already know what type of cpu it is
> running on.
>
> Can we have all this processor specific perf/counter stuff live in one place
> and simplify all of this?
[DC]: Do you mean to move init_hw_perf_events() out into perf_event.c, and
to deal with mipsxx/loongson2/rm9000/more together? If yes, that's OK.


> Too many magic numbers.  Lets have symbolic names.
[DC]: OK.


Deng-Cheng

Re: [PATCH v5 11/12] MIPS/Oprofile: use Perf-events framework as backend

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> The mips perf events system should already know what type of cpu it is
> running on.
>
> Can we have all this processor specific perf/counter stuff live in one place
> and simplify all of this?
[DC]: Do you mean to move init_hw_perf_events() out into perf_event.c, and
to deal with mipsxx/loongson2/rm9000/more together? If yes, that's OK.


> Too many magic numbers.  Lets have symbolic names.
[DC]: OK.


Deng-Cheng

Re: [PATCH v5 12/12] MIPS/Oprofile: remove old files and update Kconfig/Makefile

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> This patch could be folded into the previous one.
>
> If the previous patch really makes these unused, it shouldn't leave them
> hanging around.
[DC]: OK.


Thanks again for your time!

Deng-Cheng

Re: [PATCH v5 12/12] MIPS/Oprofile: remove old files and update Kconfig/Makefile

[Deng-Cheng Zhu]

2010/5/28 David Daney <david.s.daney@gmail.com>:
> This patch could be folded into the previous one.
>
> If the previous patch really makes these unused, it shouldn't leave them
> hanging around.
[DC]: OK.


Thanks again for your time!

Deng-Cheng

Re: [PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx)

[David Daney]

On 05/28/2010 08:10 PM, Deng-Cheng Zhu wrote:
> 2010/5/28 David Daney<david.s.daney@gmail.com>:
>    
>> General comments:
>>
>> Can you separate the code that reads and writes the performance counter
>> registers from the definitions of the various counters themselves?
>>      
> [DC]:
> 1) Do you mean to move M_PERFCTL_* stuff out into pmu.h (or mipsregs.h)?
> If yes, that's OK. Again (my reply for [1/12] mentions this for the 1st
> time): After making Oprofile use Perf-events as backend (patches 8~12 do
> this), register definitions and read/write functions will locate in pmu.h
> (or mipsregs.h) and perf_event_$cpu.c, respectively.
> 2) According to your reply to [7/12], do you mean the perf counter
> read/write functions (such as mipsxx_pmu_read_counter()) are generic
> support functions? No, they are specific for mipsxx CPUs.
>
>    


Basically what I had in mind is that for all MIPS CPUs that have this 
style of performance counters, the counters are all read in the same 
manner (by reading the c0_PerfCnt registers).  However each CPU type has 
its own set of events that can be counted.

So I was thinking to separate the common code that accesses the 
registers from the CPU specific code that deals with the specific names 
and properties of the various events.


David Daney

Re: [PATCH v5 01/12] MIPS/Oprofile: extract PMU defines/helper functions for sharing

[David Daney]

On 05/28/2010 08:06 PM, Deng-Cheng Zhu wrote:
> Hi, David
>
>
> Thanks for your comments! I'm replying to you in the patch order. If my
> comments are wrong or are bad ideas, please point out.
>
>
> 2010/5/28 David Daney<david.s.daney@gmail.com>:
>    
>> Why predicate the entire contents of the file?
>>
>> In any event, if you keep it, it shold probably be something like:
>>
>>     #if defined(CONFIG_CPU_MIPSR1) || defined(CONFIG_CPU_MIPSR2)
>>      
> [DC]:
> 1) This line is not for the "entire" contents of the file, other CPUs
> LOONGSON2 and RM9000 are here.
>    

In any event I think you want defined(CONFIG_CPU_MIPSR1) || 
defined(CONFIG_CPU_MIPSR2) instead of what you had.

> 2) The CONFIG_CPU* came from the Makefile of oprofile. If other CPUs are
> newly supported, we can add into the #if #elif.
>    

TOO_MANY_#IF == BAD.  You are rewriting the code here, you can take the 
opportunity to improve it.

> 3) The perf counter helper functions are special to mipsxx/loongson2/rm9000
> espcially the reset_counter() will be implemented respectively. Although
> they will be moved to perf_event_$cpu.c when Oprofile uses Perf-events as
> backend, they are currently shared by Oprofile and Perf-events to reduce
> code copying.
>
>
>    
>> Some or all of that should probably go in asm/mipsregs.h
>>      
> [DC]: Now that we create pmu.h and these #define's are originally in
> op_model_$cpu.c not in mipsregs.h, how about keeping them here? BTW, after
> making Oprofile use Perf-events as backend (patches 8~12 do this), pmu.h
> will only contain register definitions (no static function definitions),
> then we can consider deleting pmu.h and moving its contents to mipsregs.h,
> is it OK?
>
>    

I don't have super strong preferences for where the bit definitions for 
cop0 registers go.  To date most are in mipsregs.h.  Perhaps Ralf has a 
preference.
>> Are 0 and 1 really the only conceivable values?
>>      
> [DC]: This is also from Oprofile. If we use:
> #define vpe_id()       (cpu_has_mipsmt_pertccounters ? \
>                         0 : cpu_data[smp_processor_id()].vpe_id)
> The possible return value is supposed to be 0 or 1.
>    

I haven't read the architecture specification for the multithread ASE.  
Is it really true that exactly two VPEs is all that is allowed?  If so 
this seems fine, otherwise it should reflect the full range of allowed 
values.

David Daney