* [PATCH] EMMA2RH: tivial cleanups
@ 2010-06-17 11:33 Shinya Kuribayashi
2010-06-17 11:35 ` [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE Shinya Kuribayashi
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Shinya Kuribayashi @ 2010-06-17 11:33 UTC (permalink / raw)
To: linux-mips
Hi,
Today I was going to prepare a patch titled '[PATCH] MIPS: Move EMMA2RH
Makefile to its own Platform file', fetched and took a look at -queue
repo, and found that Ralf already fixed it up! Many thanks, Ralf :-)
So here're remaining trivial cleanups supposed to be sent along with
the Platform patch. In the future, I'm planning to sort out interrupt
routines first, PCI driver generization, and more, but I still couldn't
find enough spare time for it. I'll try my best (I'd likt to play with
the latest kernel, anyway).
Shinya Kuribayashi (4):
MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE
MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE
MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n)
MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n)
arch/mips/emma/markeins/irq.c | 8 ++--
arch/mips/include/asm/emma/emma2rh.h | 84 ++++-----------------------------
arch/mips/include/asm/emma/markeins.h | 37 +-------------
3 files changed, 16 insertions(+), 113 deletions(-)
P.S. Feel free to squash!
--
Shinya Kuribayashi
Renesas Electronics
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE
2010-06-17 11:33 [PATCH] EMMA2RH: tivial cleanups Shinya Kuribayashi
@ 2010-06-17 11:35 ` Shinya Kuribayashi
2010-07-06 14:37 ` Ralf Baechle
2010-06-17 11:36 ` [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE Shinya Kuribayashi
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Shinya Kuribayashi @ 2010-06-17 11:35 UTC (permalink / raw)
To: linux-mips
For historical reasons, we used to put MIPS CPU IRQs behind SoC-specific
IRQs in the queue, and have been using CPU_IRQ_BASE as MIPS_CPU_IRQ_BASE.
In recent years, however, we've brought it back to normal order, and now
CPU_IRQ_BASE just redefines the generic MIPS_CPU_IRQ_BASE.
At the same time, NUM_CPU_IRQ is also removed as useless.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
---
arch/mips/emma/markeins/irq.c | 8 ++++----
arch/mips/include/asm/emma/emma2rh.h | 4 +---
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9504b7e..1d1c806 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
- setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+ setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)
@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
- do_IRQ(CPU_IRQ_BASE + 7);
+ do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else if (pending & STATUSF_IP2)
emma2rh_irq_dispatch();
else if (pending & STATUSF_IP1)
- do_IRQ(CPU_IRQ_BASE + 1);
+ do_IRQ(MIPS_CPU_IRQ_BASE + 1);
else if (pending & STATUSF_IP0)
- do_IRQ(CPU_IRQ_BASE + 0);
+ do_IRQ(MIPS_CPU_IRQ_BASE + 0);
else
spurious_interrupt();
}
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 2afb2fe..fcc0064 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -99,12 +99,10 @@
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
-#define NUM_CPU_IRQ 8
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
-#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
-#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
+#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/*
* emma2rh irq defs
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE
2010-06-17 11:33 [PATCH] EMMA2RH: tivial cleanups Shinya Kuribayashi
2010-06-17 11:35 ` [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE Shinya Kuribayashi
@ 2010-06-17 11:36 ` Shinya Kuribayashi
2010-07-06 14:38 ` Ralf Baechle
2010-06-17 11:36 ` [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n) Shinya Kuribayashi
2010-06-17 11:37 ` [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n) Shinya Kuribayashi
3 siblings, 1 reply; 9+ messages in thread
From: Shinya Kuribayashi @ 2010-06-17 11:36 UTC (permalink / raw)
To: linux-mips
Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts,
current EMMA2RH plat_irq_dispatch() supports IP2 only. We can make it
configurable in the future, but for the time being, would like to make
things explicitly allcated to IP2 in accordance with plat_irq_dispatch().
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
---
arch/mips/emma/markeins/irq.c | 2 +-
arch/mips/include/asm/emma/emma2rh.h | 1 -
2 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 1d1c806..3a96799 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
- setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+ setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index fcc0064..95d0b7e 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -101,7 +101,6 @@
#define NUM_EMMA2RH_IRQ 96
-#define CPU_EMMA2RH_CASCADE 2
#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/*
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n)
2010-06-17 11:33 [PATCH] EMMA2RH: tivial cleanups Shinya Kuribayashi
2010-06-17 11:35 ` [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE Shinya Kuribayashi
2010-06-17 11:36 ` [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE Shinya Kuribayashi
@ 2010-06-17 11:36 ` Shinya Kuribayashi
2010-07-06 14:38 ` Ralf Baechle
2010-06-17 11:37 ` [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n) Shinya Kuribayashi
3 siblings, 1 reply; 9+ messages in thread
From: Shinya Kuribayashi @ 2010-06-17 11:36 UTC (permalink / raw)
To: linux-mips
Don't duplicate worthless lines.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
---
arch/mips/include/asm/emma/emma2rh.h | 79 +++-----------------------------
arch/mips/include/asm/emma/markeins.h | 4 +-
2 files changed, 10 insertions(+), 73 deletions(-)
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 95d0b7e..c1449d2 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -107,77 +107,14 @@
* emma2rh irq defs
*/
-#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
-
-#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
-#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
-#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
-#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
-#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
-#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
+#define EMMA2RH_IRQ_INT(n) (EMMA2RH_IRQ_BASE + (n))
+
+#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT(49)
+#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT(50)
+#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT(51)
+#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT(56)
+#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT(57)
+#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT(58)
/*
* EMMA2RH Register Access
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 2618bf2..507f125 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -25,8 +25,8 @@
#define NUM_EMMA2RH_IRQ_SW 32
#define NUM_EMMA2RH_IRQ_GPIO 32
-#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
+#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
+#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n)
2010-06-17 11:33 [PATCH] EMMA2RH: tivial cleanups Shinya Kuribayashi
` (2 preceding siblings ...)
2010-06-17 11:36 ` [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n) Shinya Kuribayashi
@ 2010-06-17 11:37 ` Shinya Kuribayashi
2010-07-06 14:38 ` Ralf Baechle
3 siblings, 1 reply; 9+ messages in thread
From: Shinya Kuribayashi @ 2010-06-17 11:37 UTC (permalink / raw)
To: linux-mips
Don't duplicate worthless lines.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
---
arch/mips/include/asm/emma/markeins.h | 33 +--------------------------------
1 files changed, 1 insertions(+), 32 deletions(-)
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 507f125..bf2d229 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -31,38 +31,7 @@
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
-#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT(n) (EMMA2RH_SW_IRQ_BASE + (n))
#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE
2010-06-17 11:35 ` [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE Shinya Kuribayashi
@ 2010-07-06 14:37 ` Ralf Baechle
0 siblings, 0 replies; 9+ messages in thread
From: Ralf Baechle @ 2010-07-06 14:37 UTC (permalink / raw)
To: Shinya Kuribayashi; +Cc: linux-mips
Queued for 2.6.36. Thanks, Shinya-San!
Ralf
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE
2010-06-17 11:36 ` [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE Shinya Kuribayashi
@ 2010-07-06 14:38 ` Ralf Baechle
0 siblings, 0 replies; 9+ messages in thread
From: Ralf Baechle @ 2010-07-06 14:38 UTC (permalink / raw)
To: Shinya Kuribayashi; +Cc: linux-mips
Queued for 2.6.36. Thanks, Shinya-San!
Ralf
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n)
2010-06-17 11:36 ` [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n) Shinya Kuribayashi
@ 2010-07-06 14:38 ` Ralf Baechle
0 siblings, 0 replies; 9+ messages in thread
From: Ralf Baechle @ 2010-07-06 14:38 UTC (permalink / raw)
To: Shinya Kuribayashi; +Cc: linux-mips
Queued for 2.6.36. Thanks, Shinya-San!
Ralf
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n)
2010-06-17 11:37 ` [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n) Shinya Kuribayashi
@ 2010-07-06 14:38 ` Ralf Baechle
0 siblings, 0 replies; 9+ messages in thread
From: Ralf Baechle @ 2010-07-06 14:38 UTC (permalink / raw)
To: Shinya Kuribayashi; +Cc: linux-mips
Queued for 2.6.36. Thanks, Shinya-San!
Ralf
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2010-07-06 14:39 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2010-06-17 11:33 [PATCH] EMMA2RH: tivial cleanups Shinya Kuribayashi
2010-06-17 11:35 ` [PATCH 1/4] MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE Shinya Kuribayashi
2010-07-06 14:37 ` Ralf Baechle
2010-06-17 11:36 ` [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE Shinya Kuribayashi
2010-07-06 14:38 ` Ralf Baechle
2010-06-17 11:36 ` [PATCH 3/4] MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n) Shinya Kuribayashi
2010-07-06 14:38 ` Ralf Baechle
2010-06-17 11:37 ` [PATCH 4/4] MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n) Shinya Kuribayashi
2010-07-06 14:38 ` Ralf Baechle
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