From: David Daney <ddaney@caviumnetworks.com>
To: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org,
linux-kernel@vger.kernel.org,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@elte.hu>,
Arnaldo Carvalho de Melo <acme@redhat.com>
Subject: Re: [PATCH 5/6] MIPS: perf: Add support for 64-bit perf counters.
Date: Thu, 20 Jan 2011 09:48:53 -0800 [thread overview]
Message-ID: <4D387585.8020705@caviumnetworks.com> (raw)
In-Reply-To: <AANLkTi=8NndFv6czWy1q_iDvJRHhCYYu06fhyBL9ByE=@mail.gmail.com>
On 01/20/2011 02:06 AM, Deng-Cheng Zhu wrote:
> 2011/1/7 David Daney<ddaney@caviumnetworks.com>:
>> @@ -294,14 +519,29 @@ static void mipspmu_read(struct perf_event *event)
>>
>> static void mipspmu_enable(struct pmu *pmu)
>> {
>> - if (mipspmu)
>> - mipspmu->start();
>> +#ifdef CONFIG_MIPS_MT_SMP
>> + write_unlock(&pmuint_rwlock);
>> +#endif
>> + resume_local_counters();
>> }
>
> When working with CONFIG_MIPS_MT_SMP, the compiler says 'pmuint_rwlock
> undeclared' because of its improper place of definition.
>
OK, I will try to fix it.
>
>> @@ -1550,10 +1462,30 @@ init_hw_perf_events(void)
>> return -ENODEV;
>> }
>>
>> - if (mipspmu)
>> - pr_cont("%s PMU enabled, %d counters available to each "
>> - "CPU, irq %d%s\n", mipspmu->name, counters, irq,
>> - irq< 0 ? " (share with timer interrupt)" : "");
>> + mipspmu.num_counters = counters;
>> + mipspmu.irq = irq;
>> +
>> + if (read_c0_perfctrl0()& M_PERFCTL_WIDE) {
>> + mipspmu.max_period = (1ULL<< 63) - 1;
>> + mipspmu.valid_count = (1ULL<< 63) - 1;
>> + mipspmu.overflow = 1ULL<< 63;
>> + mipspmu.read_counter = mipsxx_pmu_read_counter_64;
>> + mipspmu.write_counter = mipsxx_pmu_write_counter_64;
>> + counter_bits = 64;
>> + } else {
>> + mipspmu.max_period = (1ULL<< 32) - 1;
>> + mipspmu.valid_count = (1ULL<< 31) - 1;
>> + mipspmu.overflow = 1ULL<< 31;
>> + mipspmu.read_counter = mipsxx_pmu_read_counter;
>> + mipspmu.write_counter = mipsxx_pmu_write_counter;
>> + counter_bits = 32;
>> + }
>> +
>> + on_each_cpu(reset_counters, (void *)(long)counters, 1);
>> +
>> + pr_cont("%s PMU enabled, %d %d-bit counters available to each "
>> + "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
>> + irq< 0 ? " (share with timer interrupt)" : "");
>>
>> perf_pmu_register(&pmu);
>>
>
> perf_pmu_register(&pmu) should be now changed to perf_pmu_register(&pmu,
> "cpu", PERF_TYPE_RAW).
Yes, I already have that locally.
David Daney
next prev parent reply other threads:[~2011-01-20 17:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-07 2:35 [PATCH 0/6] MIPS: perf: Make perf work for 64-bit/Octeon counters David Daney
2011-01-07 2:35 ` [PATCH 1/6] MIPS: Octeon: Enable per-CPU IRQs on all CPUs David Daney
2011-01-07 2:35 ` [PATCH 2/6] MIPS: Add accessor macros for 64-bit performance counter registers David Daney
2011-01-07 2:35 ` [PATCH 3/6] MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c David Daney
2011-01-07 2:35 ` [PATCH 4/6] MIPS: perf: Reorganize contents of perf support files David Daney
2011-01-20 10:01 ` Deng-Cheng Zhu
2011-01-20 17:51 ` David Daney
2011-01-07 2:35 ` [PATCH 5/6] MIPS: perf: Add support for 64-bit perf counters David Daney
2011-01-20 10:06 ` Deng-Cheng Zhu
2011-01-20 17:48 ` David Daney [this message]
2011-01-07 2:35 ` [PATCH 6/6] MIPS: perf: Add Octeon support for hardware perf David Daney
2011-01-20 9:59 ` [PATCH 0/6] MIPS: perf: Make perf work for 64-bit/Octeon counters Deng-Cheng Zhu
2011-01-20 17:55 ` David Daney
2011-01-22 0:17 ` David Daney
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