From: David Daney <david.s.daney@gmail.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Ralf Baechle <ralf@linux-mips.org>,
David Daney <ddaney@caviumnetworks.com>,
linux-mips@linux-mips.org
Subject: Re: [patch 3/5] MIPS: Octeon: Simplify irq_cpu_on/offline irq chip functions
Date: Sun, 27 Mar 2011 17:24:38 -0700 [thread overview]
Message-ID: <4D8FD546.7090806@gmail.com> (raw)
In-Reply-To: <alpine.LFD.2.00.1103272326270.31464@localhost6.localdomain6>
On 03/27/2011 02:29 PM, Thomas Gleixner wrote:
> On Sun, 27 Mar 2011, David Daney wrote:
>
>> On 03/27/2011 09:22 AM, Thomas Gleixner wrote:
>>> Make use of the IRQCHIP_ONOFFLINE_ENABLED flag and remove the
>>> wrappers. Use irqd_irq_disabled() instead of desc->status, which will
>>> go away.
>>>
>> I rewrote my patch set and was testing it. Interesting that I came up with a
>> function with almost the same name and purpose.
>>
>> However my function told us if the irq was masked *or* disabled. The idea
>> being a function that returns true if the irq could fire. We cannot be
>> enabling the interrupt in the controller if it is masked.
>>
>> For example I need to test this when adjusting affinity, and taking CPUs on
>> and off line.
>>
>> I don't think your genirq changes can tell the me information I really need in
>> their current state. I think we need to consider how the masked state
>> interacts with IRQCHIP_ONOFFLINE_ENABLED and irqd_irq_disabled().
>>
>> Since I have totally rewritten my interrupt code, I am a bit ambivalent about
>> applying these patches. It might make more sense that I adjust my patch for
>> your genirq changes and test it before committing it.
> The modifications I made are 100% equivalent to the code you provided
> in the first place.
Acknowledged.
However subsequently, I made mostly equivalent changes. The main
difference is that I added IRQS_MASKED into the mix testing it in
addition to IRQS_DISABLED
> The IRQCHIP_ONOFFLINE_ENABLED flag is only used for the on/offline
> callbacks. The disabled checked based on irq_data is in the affinity
> setting code.
>
> Unless I'm missing something we should be all set.
>
As I mentioned in the other e-mail, I am concerned that some of the chip
functions may get called when the desc is in a IRQS_MASKED istate.
If we can prevent calling .irq_cpu_online when IRQS_MASKED is set that
might be good.
Perhaps adding a flag similar to IRQCHIP_ONOFFLINE_ENABLED, to disable
calling .irq_set_affinity when the irq shouldn't be enabled.
With something like that, I think we can get rid of all the checks in
the irq_chip functions.
Thanks,
David Daney
next prev parent reply other threads:[~2011-03-28 0:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-27 16:22 [patch 0/5] MIPS: Final irq fixups Thomas Gleixner
2011-03-27 16:22 ` [patch 1/5] MIPS: Fix syncfs syscall copy and paste failure Thomas Gleixner
2011-03-28 11:55 ` Ralf Baechle
2011-03-27 16:22 ` [patch 2/5] MIPS: Octeon: Rewrite interrupt handling code Thomas Gleixner
2011-03-27 16:22 ` [patch 3/5] MIPS: Octeon: Simplify irq_cpu_on/offline irq chip functions Thomas Gleixner
2011-03-27 21:12 ` David Daney
2011-03-27 21:29 ` Thomas Gleixner
2011-03-27 21:41 ` Thomas Gleixner
2011-03-28 0:12 ` David Daney
2011-03-28 0:24 ` David Daney [this message]
2011-03-27 16:22 ` [patch 4/5] MIPS: alchemy: Use proper irq accessors Thomas Gleixner
2011-03-28 12:00 ` Ralf Baechle
2011-03-27 16:22 ` [patch 5/5] MIPS: Convert the irq functions to the new names Thomas Gleixner
2011-03-28 12:01 ` Ralf Baechle
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