From: David Daney <ddaney@caviumnetworks.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [patch 2/3] MIPS: Octeon: Rewrite interrupt handling code.
Date: Mon, 28 Mar 2011 14:55:51 -0700 [thread overview]
Message-ID: <4D9103E7.1090109@caviumnetworks.com> (raw)
In-Reply-To: <20110328150627.679291180@linutronix.de>
On 03/28/2011 08:06 AM, Thomas Gleixner wrote:
> From: David Daney<ddaney@caviumnetworks.com>
>
> This includes conversion to new style irq_chip functions, and
> correctly enabling/disabling per-CPU interrupts.
>
> The hardware interrupt bit to irq number mapping is now done with a
> flexible map, instead of by bit twiddling the irq number.
>
> [ tglx: Adjusted to new irq_cpu_on/offline callbacks and
> __irq_set_affinity_lock ]
>
> Signed-off-by: David Daney<ddaney@caviumnetworks.com>
> Cc: linux-mips@linux-mips.org
> Cc: ralf@linux-mips.org
> LKML-Reference:<1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com>
> Signed-off-by: Thomas Gleixner<tglx@linutronix.de>
> ---
> arch/mips/cavium-octeon/octeon-irq.c | 1410 ++++++++++++++-----------
> arch/mips/cavium-octeon/setup.c | 12
> arch/mips/cavium-octeon/smp.c | 39
> arch/mips/include/asm/mach-cavium-octeon/irq.h | 243 +---
> arch/mips/include/asm/octeon/octeon.h | 2
> arch/mips/pci/msi-octeon.c | 20
> 6 files changed, 915 insertions(+), 811 deletions(-)
>
Well tglx modified my patch slightly, but it still works. So this one
is OK too.
David Daney
next prev parent reply other threads:[~2011-03-28 21:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-28 15:06 [patch 0/3] mips: octeon: final tweaks Thomas Gleixner
2011-03-28 15:06 ` [patch 1/3] genirq: Move INPROGRESS, MASKED and DISABLED state flags to irq_data Thomas Gleixner
2011-03-28 15:06 ` [patch 2/3] MIPS: Octeon: Rewrite interrupt handling code Thomas Gleixner
2011-03-28 21:55 ` David Daney [this message]
2011-03-28 15:06 ` [patch 3/3] MIPS: Octeon: Simplify irq_cpu_on/offline irq chip functions Thomas Gleixner
2011-03-28 21:54 ` David Daney
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