From: Sergei Shtylyov <sshtylyov@mvista.com>
To: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH] MIPS: Netlogic: Minor fixes for XLR processors
Date: Sat, 30 Jul 2011 17:46:44 +0400 [thread overview]
Message-ID: <4E340B44.3050305@mvista.com> (raw)
In-Reply-To: <20110730110449.GA30043@jayachandranc.netlogicmicro.com>
Hello.
On 30-07-2011 15:04, Jayachandran C wrote:
> * Avoid unneeded cache flushes, XLR dcache is fully coherent across
> CPUs.
> * add r4k_wait as the cpu_wait
> * Move load address - the current value wastes space.
This seems like a material for the whole 3 patches...
WBR, Sergei
prev parent reply other threads:[~2011-07-30 13:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-30 11:04 [PATCH] MIPS: Netlogic: Minor fixes for XLR processors Jayachandran C
2011-07-30 13:46 ` Sergei Shtylyov [this message]
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