From: David Daney <david.daney@cavium.com>
To: SAURABH MALPANI <saurabh140585@gmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu
Date: Tue, 06 Sep 2011 11:38:28 -0700 [thread overview]
Message-ID: <4E6668A4.8010300@cavium.com> (raw)
In-Reply-To: <CAFsuBjW4XZy6x4gDL+0cw92jUbuEodF4vzCcCijQDize97wkNQ@mail.gmail.com>
On 09/05/2011 03:23 AM, SAURABH MALPANI wrote:
> Hi,
>
> <Re sending this because last time I am afraid I didn't hit the
> correct mail filters.>
>
> Query:
>
> mailbox_interrupt is not registered with IRQF_PERCPU but it is
> supposed to be percpu interrupt. Is that on purpose or a miss?
On Octeon the per-cpuness of a particular irq is a property of the irq
itself rather than being controlled by IRQF_PERCPU. So other than being
perhaps stylistically in poor taste, no harm is done by omitting
IRQF_PERCPU here.
> I am
> porting some code from x86 to octeon which requires special handling
> for per cpu interrupts.
>
> void octeon_prepare_cpus(unsigned int max_cpus)
> {
> cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
> if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
> "mailbox0", mailbox_interrupt)) {
> panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
> }
> if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
> "mailbox1", mailbox_interrupt)) {
> panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
> }
> }
>
> --
> Saurabh
>
>
next prev parent reply other threads:[~2011-09-06 18:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-05 10:23 MIPS: Octeon: mailbox_interrupt is not registered as per cpu SAURABH MALPANI
2011-09-06 18:38 ` David Daney [this message]
2011-09-06 19:02 ` SAURABH MALPANI
2011-09-06 19:17 ` David Daney
2011-09-06 19:21 ` SAURABH MALPANI
-- strict thread matches above, loose matches on Subject: below --
2011-09-02 7:59 MIPS:Octeon: " SAURABH MALPANI
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