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From: David Daney <david.daney@cavium.com>
To: Joe Buehler <aspam@cox.net>
Cc: linux-mips@linux-mips.org
Subject: Re: using mprotect to write to .text
Date: Tue, 11 Oct 2011 11:06:11 -0700	[thread overview]
Message-ID: <4E948593.6030604@cavium.com> (raw)
In-Reply-To: <4E947D8A.9090409@cox.net>

On 10/11/2011 10:31 AM, Joe Buehler wrote:
> David Daney wrote:
>
>> No, it does nothing of the sort.  You need cacheflush() for that.
>
> OK, I looked at cacheflush and it can be used to flush the icache on all
> CPUs, which is what I want.  My current code sequence is more than that
> however.  Something like this:
>
> 	CVMX_ICACHE_INVALIDATE;

This only works if you can guarantee that the code will never be run on 
a different CPU than the current one.  For most Linux code you cannot 
make such an assertion.

> 	CVMX_SYNC;

Unneeded.

> 	uint64_t tmp;
> 	asm volatile ("    la %0,10f\n"
> 		  "    jr.hb %0\n"
> 		  "    nop\n"
> 		  "    10:\n" : "=r" (tmp) : : "memory");

jr.hb is equivalent to jr on Octeon.

>
> I can certainly modify cacheflush for my application so the extra hazard
> clearing is done when icache is flushed.  Is there any way to avoid that
> and use existing kernel functionality?
>

I cannot parse the meaning out of these last two sentences.  The 
cacheflush() system call both exists and works.  You want to change it?

David Daney

  reply	other threads:[~2011-10-11 18:06 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-10 20:02 using mprotect to write to .text Joe Buehler
2011-10-11 16:36 ` David Daney
2011-10-11 17:31   ` Joe Buehler
2011-10-11 18:06     ` David Daney [this message]
2011-10-11 18:35       ` Joe Buehler
2011-10-11 18:43         ` David Daney
2011-10-11 23:17           ` Ralf Baechle

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