From: Sergei Shtylyov <sshtylyov@mvista.com>
To: "Steven J. Hill" <sjhill@mips.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org,
sjhill@realitydiluted.com
Subject: Re: [PATCH 4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and conflicts.
Date: Fri, 06 Apr 2012 22:12:09 +0400 [thread overview]
Message-ID: <4F7F31F9.7030706@mvista.com> (raw)
In-Reply-To: <1333735183-15796-1-git-send-email-sjhill@mips.com>
Hello.
On 04/06/2012 09:59 PM, Steven J. Hill wrote:
> From: "Steven J. Hill"<sjhill@mips.com>
> Turns on PCI 2.1 compatibility for the Malta platform for the
> PIIX4 controller. Change start address to avoid conflicts with
> the ACPI and SMB devices.
> Signed-off-by: Steven J. Hill<sjhill@mips.com>
> ---
[...]
> diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
> index b7f37d4..5f7d113 100644
> --- a/arch/mips/mti-malta/malta-setup.c
> +++ b/arch/mips/mti-malta/malta-setup.c
> @@ -222,3 +222,14 @@ void __init plat_mem_setup(void)
> board_be_init = malta_be_init;
> board_be_handler = malta_be_handler;
> }
> +/* Enable PCI 2.1 compatibility in PIIX4 */
> +static void __init quirk_dlcsetup(struct pci_dev *dev)
> +{
> + u8 odlc, ndlc;
You don't need two variables. And please add an empty line after declaration
block.
> + (void) pci_read_config_byte(dev, 0x82,&odlc);
> + /* Enable passive releases and delayed transaction */
> + ndlc = odlc | 7;
> + (void) pci_write_config_byte(dev, 0x82, ndlc);
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
> + quirk_dlcsetup);
WBR, Sergei
prev parent reply other threads:[~2012-04-06 18:13 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-06 17:59 [PATCH 4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and conflicts Steven J. Hill
2012-04-06 18:12 ` Sergei Shtylyov [this message]
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