From: Sergei Shtylyov <sshtylyov@mvista.com>
To: "Steven J. Hill" <sjhill@mips.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH v2,1/5] MIPS: Add support for the 1074K core.
Date: Sat, 12 May 2012 16:09:24 +0400 [thread overview]
Message-ID: <4FAE52F4.6020301@mvista.com> (raw)
In-Reply-To: <1336684439-25109-1-git-send-email-sjhill@mips.com>
Hello.
On 11-05-2012 1:13, Steven J. Hill wrote:
> From: "Steven J. Hill"<sjhill@mips.com>
> This patch adds support for detecting and using 1074K cores.
> Signed-off-by: Steven J. Hill<sjhill@mips.com>
[...]
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index bda8eb2..c646a79 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
> c->icache.linesz = 2<< lsize;
> else
> c->icache.linesz = lsize;
> - c->icache.sets = 64<< ((config1>> 22)& 7);
> + c->icache.sets = 32<< (((config1>> 22) + 1)& 7);
> c->icache.ways = 1 + ((config1>> 16)& 7);
>
> icache_size = c->icache.sets *
> @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
> c->dcache.linesz = 2<< lsize;
> else
> c->dcache.linesz= lsize;
> - c->dcache.sets = 64<< ((config1>> 13)& 7);
> + c->dcache.sets = 32<< (((config1>> 13) + 1)& 7);
> c->dcache.ways = 1 + ((config1>> 7)& 7);
Are these related changes? They seem common, no 1074K specific...
> @@ -1051,9 +1051,26 @@ static void __cpuinit probe_pcache(void)
> case CPU_R14000:
> break;
>
> + case CPU_74K:
> + /*
> + * Early versions of the 74k do not update
Early versions of 74K and 1074K? Shouldn't this be a sperate patch?
> + * the cache tags on a vtag miss/ptag hit
> + * which can occur in the case of KSEG0/KUSEG aliases
> + * In this case it is better to treat the cache as always
> + * having aliases
> + */
> + if ((c->processor_id& 0xff)<= PRID_REV_ENCODE_332(2, 4, 0))
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + if ((c->processor_id& 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + if (((c->processor_id& 0xff00) == PRID_IMP_1074K)&&
> + ((c->processor_id& 0xff)<= PRID_REV_ENCODE_332(1, 1, 0))) {
> + c->dcache.flags |= MIPS_CACHE_VTAG;
> + write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> + }
> + /* fall through */
> case CPU_24K:
> case CPU_34K:
> - case CPU_74K:
> case CPU_1004K:
> if ((read_c0_config7()& (1<< 16))) {
> /* effectively physically indexed dcache,
> diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
> index 54759f1..53bbe55 100644
> --- a/arch/mips/oprofile/op_model_mipsxx.c
> +++ b/arch/mips/oprofile/op_model_mipsxx.c
> @@ -330,12 +330,6 @@ static int __init mipsxx_init(void)
> break;
>
> case CPU_1004K:
> -#if 0
> - /* FIXME: report as 34K for now */
> - op_model_mipsxx_ops.cpu_type = "mips/1004K";
> - break;
> -#endif
> -
Unrelated change.
WBR, Sergei
next prev parent reply other threads:[~2012-05-12 12:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-10 21:13 [PATCH v2,1/5] MIPS: Add support for the 1074K core Steven J. Hill
2012-05-12 12:09 ` Sergei Shtylyov [this message]
2012-05-21 15:38 ` Hill, Steven
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