Re: Linux port failing on MIPS32 24Kc

[joe seb <joe.seb8@gmail.com>]

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Hi David, Ralf,

This is a new FPGA based platform which has MIPS 24k core and we are trying
to bring up linux on this. MIPS cpu is running at 50MHz.

Other than ram, we have UART available and its a 8250 compatible UART which
is connected to one of the HW interrupt line. The MIPS timer interrupt is
connected to HW4 interrupt line.  So in our platform file, we provide the
irq dispatch function for these two irq lines. There is no driver which uses
the DMA.

We did another experiment where we replaced init application with a memory
test code which malloc and run incremental pattern test on the allocated
memory and we see sometimes this test is failing. The failure is happening
for a cache line, when we dump ddr corresponding to that cache line, we see
that, that particular cache line is not flushed to ddr and all the other
cache lines are fine. So, not sure any issue with flushing the write-back.
We checked the linux code and did not see any place dcache is flushed for a
particular line, its always for a page(blast_dcache functions). Is our
finding correct?

Regards,
Joe

On Wed, Jul 8, 2009 at 11:59 PM, David VomLehn <dvomlehn@cisco.com> wrote:

> On Wed, Jul 08, 2009 at 06:17:42PM +0530, joe seb wrote:
> > Hi,
> >
> > We made the following changes and tried,
> >
> > -> applied the patch given by you.
> > -> changed the PHYS_OFFSET to 0x10000000 to match our memory offset.
> > -> cache write back mode enabled
> >
> > Still we face the same problem. It crashes at different points when it
> > enters the user space. I have attached one of the logs.
> >
> > But in cache write through mode it works.
>
> Another thought: if it works with write through, but not write back, you
> may have a device driver that isn't flushing/invalidating cache
> appropriately
> before doing DMA. This is much more important on MIPS than many other
> processors.
>
> Is this a new platform or one that has been working for a while?
>
> David VomLehn
>

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