From: Sergei Shtylyov <sshtylyov@mvista.com>
To: John Crispin <blogic@openwrt.org>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay
Date: Sun, 22 Jul 2012 20:04:40 +0400 [thread overview]
Message-ID: <500C2498.1010609@mvista.com> (raw)
In-Reply-To: <1342940161-1421-2-git-send-email-blogic@openwrt.org>
Hello.
On 22-07-2012 10:55, John Crispin wrote:
> The PCI core has a register that allows us to set the nanosecond delay of the
> PCI clock lane. This patch adds a helper function to allow setting this value.
> Signed-off-by: John Crispin <blogic@openwrt.org>
[...]
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index befbb76..91bb435 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
[...]
> @@ -258,6 +262,16 @@ static void clkdev_add_pci(void)
> clkdev_add(&clk_ext->cl);
> }
>
> +/* allow PCI driver to specify the clock delay. This is a 6 bit value */
WHy make it 'u32' then?
> +void ltq_pci_set_delay(u32 delay)
> +{
> + u32 val = ltq_cgu_r32(pcicr);
> +
> + val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT);
> + val |= (delay & PCI_DLY_MASK) << PCI_DLY_SHIFT;
> + ltq_cgu_w32(val, pcicr);
> +}
> +
WBR, Sergei
next prev parent reply other threads:[~2012-07-22 16:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-22 6:55 [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset John Crispin
2012-07-22 6:55 ` [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay John Crispin
2012-07-22 16:04 ` Sergei Shtylyov [this message]
2012-07-22 16:08 ` John Crispin
2012-07-22 6:55 ` [PATCH 3/5] MIPS: lantiq: make use of new PCI clock helper John Crispin
2012-07-22 6:56 ` [PATCH 4/5] MIPS: lantiq: adds device_tree_init function John Crispin
2012-07-22 6:56 ` [PATCH 5/5] MIPS: lantiq: platform specific CLK fixup John Crispin
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