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[91.76.88.205]) by mx.google.com with ESMTPSA id p16sm917580lbi.13.2013.06.05.13.01.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Jun 2013 13:01:34 -0700 (PDT) Message-ID: <51AF9923.7000606@cogentembedded.com> Date: Thu, 06 Jun 2013 00:01:39 +0400 From: Sergei Shtylyov Organization: Cogent Embedded User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 To: "Steven J. Hill" CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception bit. References: <1370461798-20296-1-git-send-email-Steven.Hill@imgtec.com> In-Reply-To: <1370461798-20296-1-git-send-email-Steven.Hill@imgtec.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Gm-Message-State: ALoCoQnr1E04yDITEkrL+wd2EO7JVew1jq5auZWE1VophRUQ7McoXPydzeryF/BaKNkgu3kQWlum Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 36704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sergei.shtylyov@cogentembedded.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Hello. On 06/05/2013 11:49 PM, Steven J. Hill wrote: > The ISA exception bit selects whether exceptions are taken in classic > or microMIPS mode. This bit is Config3.ISAOnExc and was improperly > defined as bits 16 and 17 instead of just bit 16. A new function was > added so that platforms could set this bit when running a kernel > compiled with only microMIPS instructions. Ahem, isn't that function a material for another patch? > Signed-off-by: Steven J. Hill > --- > Changes from v5: > * Make 'set_micromips_exception_mode' function to always be called. > > arch/mips/include/asm/mipsregs.h | 18 +++++++++++++++++- > arch/mips/kernel/cpu-probe.c | 3 --- > arch/mips/kernel/traps.c | 5 +++++ > 3 files changed, 22 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h > index 87e6207..cc0f5d7 100644 > --- a/arch/mips/include/asm/mipsregs.h > +++ b/arch/mips/include/asm/mipsregs.h > @@ -596,7 +596,7 @@ > #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) > #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) > #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) > -#define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16) > +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) > #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) > > #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) > @@ -1161,6 +1161,22 @@ do { \ > #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) > > /* > + * Set exceptions to be taken in microMIPS mode only, otherwise > + * set for classic exceptions. > + */ > +static inline void set_micromips_exception_mode(void) > +{ > + unsigned int config3 = read_c0_config3(); > + > +#ifdef CONFIG_CPU_MICROMIPS > + if (config3 & MIPS_CONF3_ISA) > + write_c0_config3(config3 | MIPS_CONF3_ISA_OE); > + else > +#endif > + write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); > +} > + > +/* > * Macros to access the floating point coprocessor control registers > */ > #define read_32bit_cp1_register(source) \ [...] > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index a75ae40..151ed59 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1837,6 +1837,11 @@ void __init trap_init(void) > ebase += (read_c0_ebase() & 0x3ffff000); > } > > + /* > + * Set microMIPS exceptions for platforms that support it. > + */ > + set_micromips_exception_mode(); If we have reduced the call sites to 1, do we still need the function? :-) WBR, Sergei