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Date:   Wed, 5 Jun 2013 16:36:28 -0500
From:   "Steven J. Hill" <Steven.Hill@imgtec.com>
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To:     Jonas Gorski <jogo@openwrt.org>
CC:     David Daney <ddaney.cavm@gmail.com>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception
 bit.
References: <1370461798-20296-1-git-send-email-Steven.Hill@imgtec.com> <51AFA540.5010207@gmail.com> <51AFAA8C.6080002@imgtec.com> <CAOiHx=mFqC=GN0jmb9PXpt+JapfWoP3Pu5NM0sp=F_uAZuwUEA@mail.gmail.com>
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On 06/05/2013 04:23 PM, Jonas Gorski wrote:
>
> 	if (cpu_has_mmips) {
> 		unsigned int config3 = read_c0_config3();
>
> 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
> 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> 		else
> 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
> 	}
>
>
I like this being in 'trap_init' instead. Any objections?

From mboxrd@z Thu Jan  1 00:00:00 1970
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Message-ID: <51AFAF5C.3020109@imgtec.com>
Date: Wed, 5 Jun 2013 16:36:28 -0500
From: "Steven J. Hill" <Steven.Hill@imgtec.com>
MIME-Version: 1.0
Subject: Re: [PATCH v6] MIPS: micromips: Fix improper definition of ISA exception
 bit.
References: <1370461798-20296-1-git-send-email-Steven.Hill@imgtec.com> <51AFA540.5010207@gmail.com> <51AFAA8C.6080002@imgtec.com> <CAOiHx=mFqC=GN0jmb9PXpt+JapfWoP3Pu5NM0sp=F_uAZuwUEA@mail.gmail.com>
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To: Jonas Gorski <jogo@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>, linux-mips@linux-mips.org
Message-ID: <20130605213628.10wqNUzh1O93EjqGKLv6qUbPEJlLyaZeSu7yiqQ2vxU@z>

On 06/05/2013 04:23 PM, Jonas Gorski wrote:
>
> 	if (cpu_has_mmips) {
> 		unsigned int config3 = read_c0_config3();
>
> 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
> 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
> 		else
> 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
> 	}
>
>
I like this being in 'trap_init' instead. Any objections?