From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: "Steven J. Hill" <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org,
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>,
ralf@linux-mips.org
Subject: Re: [PATCH] MIPS: Add missing hazard barrier in TLB load handler.
Date: Thu, 20 Jun 2013 15:13:57 +0400 [thread overview]
Message-ID: <51C2E3F5.7040507@cogentembedded.com> (raw)
In-Reply-To: <1371707874-6632-1-git-send-email-Steven.Hill@imgtec.com>
Hello.
On 20-06-2013 9:57, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> MIPS R2 documents state that an execution hazard barrier is needed
> after a TLBR before reading EntryLo.
> Change-Id: Idef3b6abbb63a1bbd5e153c6110a979fa7bd5896
Sigh...
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
> arch/mips/mm/tlbex.c | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index d9969d2..5ef426c 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -1922,6 +1922,11 @@ static void build_r4000_tlb_load_handler(void)
> uasm_i_nop(&p);
>
> uasm_i_tlbr(&p);
> +#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
Suggesting to use if (!IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON)) to
avoid #ifdef...
> + /* hazard barrier after TLBR but before read EntryLo */
> + if (cpu_has_mips_r2)
> + uasm_i_ehb(&p);
> +#endif
> /* Examine entrylo 0 or 1 based on ptr. */
> if (use_bbit_insns()) {
> uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
> @@ -1976,6 +1981,11 @@ static void build_r4000_tlb_load_handler(void)
> uasm_i_nop(&p);
>
> uasm_i_tlbr(&p);
> +#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
Same here.
> + /* hazard barrier after TLBR but before read EntryLo */
> + if (cpu_has_mips_r2)
> + uasm_i_ehb(&p);
> +#endif
WBR, Sergei
next prev parent reply other threads:[~2013-06-20 11:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 5:57 [PATCH] MIPS: Add missing hazard barrier in TLB load handler Steven J. Hill
2013-06-20 11:07 ` Ralf Baechle
2013-06-20 11:13 ` Sergei Shtylyov [this message]
2013-06-20 13:32 ` Ralf Baechle
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