From: Gabor Juhos <juhosg@openwrt.org>
To: John Crispin <blogic@openwrt.org>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH 2/5] MIPS: ralink: mt7620: add spi clock definition
Date: Wed, 14 Aug 2013 18:34:59 +0200 [thread overview]
Message-ID: <520BB1B3.5000400@openwrt.org> (raw)
In-Reply-To: <1375960672-32619-2-git-send-email-blogic@openwrt.org>
2013.08.08. 13:17 keltezéssel, John Crispin írta:
> The definition of the spi clock is missing.
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> arch/mips/ralink/mt7620.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
> index ccdec5a..769296f 100644
> --- a/arch/mips/ralink/mt7620.c
> +++ b/arch/mips/ralink/mt7620.c
> @@ -167,6 +167,7 @@ void __init ralink_clk_init(void)
> ralink_clk_add("cpu", cpu_rate);
> ralink_clk_add("10000100.timer", 40000000);
> ralink_clk_add("10000500.uart", 40000000);
> + ralink_clk_add("10000b00.spi", 40000000);
Please verify this. The SPI core uses the system clock AFAIK.
-Gabor
next prev parent reply other threads:[~2013-08-14 16:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-08 11:17 [PATCH 1/5] MIPS: ralink: mt7620: add verbose ram info John Crispin
2013-08-08 11:17 ` [PATCH 2/5] MIPS: ralink: mt7620: add spi clock definition John Crispin
2013-08-14 16:34 ` Gabor Juhos [this message]
2013-08-08 11:17 ` [PATCH 3/5] MIPS: ralink: mt7620: add wdt " John Crispin
2013-08-08 11:17 ` [PATCH 4/5] MIPS: ralink: mt7620: fix usb issue during frequency scaling John Crispin
2013-08-08 11:17 ` [PATCH 5/5] MIPS: ralink: mt7620: this SoC has ehci and ohci hosts John Crispin
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