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Date:   Sat, 11 Jan 2014 11:45:28 +0100
From:   John Crispin <blogic@openwrt.org>
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To:     Florian Fainelli <florian@openwrt.org>
CC:     linux-mips@linux-mips.org, ralf@linux-mips.org, jogo@openwrt.org,
        mbizon@freebox.fr, cernekee@gmail.com, dgcbueu@gmail.com
Subject: Re: [PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT
 value
References: <1389386114-31834-1-git-send-email-florian@openwrt.org> <1389386114-31834-4-git-send-email-florian@openwrt.org>
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On 10/01/14 21:35, Florian Fainelli wrote:
> Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
> value of 4) instead of the currently configured 32 bytes L1-cache line
> size.
>
> Reported-by: Daniel Gonzalez<dgcbueu@gmail.com>
> Signed-off-by: Florian Fainelli<florian@openwrt.org>
> ---
>   arch/mips/Kconfig | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 123f7c0..a3fec87 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -139,6 +139,7 @@ config BCM63XX
>   	select SWAP_IO_SPACE
>   	select ARCH_REQUIRE_GPIOLIB
>   	select HAVE_CLK
> +	select MIPS_L1_CACHE_SHIFT_4
>   	help
>   	 Support for BCM63XX based boards
>


Hi Florian,

why is this not part of 1/3

     John