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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: John Crispin <blogic@openwrt.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH 1/2] DT: Add documentation for gpio-rt2880
Date: Fri, 10 Oct 2014 16:37:34 +0400	[thread overview]
Message-ID: <5437D30E.6030602@cogentembedded.com> (raw)
In-Reply-To: <54376E45.8020904@openwrt.org>

On 10/10/2014 9:27 AM, John Crispin wrote:

    Hm, why didn't you reply to me but only to linux-mips?

>>> +- interrupts : Specify the INTC interrupt number +-
>>> ralink,num-gpios : Specify the number of GPIOs +-
>>> ralink,register-map : The register layout depends on the GPIO
>>> bank and actual +        SoC type. Register offsets need to be in
>>> this order. +        [ INT, EDGE, RENA, FENA, DATA, DIR, POL,
>>> SET, RESET, TOGGLE ]

>> This should be determined by the "compatible" property alone, I
>> think.

> we specifically put this into dts as almost each of the SoC versions
> has a different register layout. i really want to avoid having to
> patch the gpio driver whenever ralink/mtk decides to "change the
> registers yet again".

    Yes, that's what we have to do in e.g. driver/net/ethernet/sh_eth.c.
There are 5 register layouts known by now, 2 of them were added recently. :-)

> I can change it if must be.

    Yes, I think it must be this way.

> but i really would
> prefer to keep it this way as it will safe me lots of time in future

> 	John

WBR, Sergei

  reply	other threads:[~2014-10-10 12:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-09 20:07 [PATCH 1/2] DT: Add documentation for gpio-rt2880 John Crispin
2014-10-09 20:07 ` [PATCH 2/2] GPIO: MIPS: ralink: add gpio driver for ralink SoC John Crispin
2014-10-27 16:36   ` Linus Walleij
2014-10-09 20:30 ` [PATCH 1/2] DT: Add documentation for gpio-rt2880 Sergei Shtylyov
2014-10-10  5:27   ` John Crispin
2014-10-10 12:37     ` Sergei Shtylyov [this message]
2014-10-10 13:31 ` John Crispin

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