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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: "Steven J. Hill" <Steven.Hill@imgtec.com>, linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
Subject: Re: [PATCH 06/11] MIPS: Add CP0 macros for extended EntryLo registers
Date: Thu, 13 Nov 2014 15:25:32 +0300	[thread overview]
Message-ID: <5464A33C.1060502@cogentembedded.com> (raw)
In-Reply-To: <1415858743-24492-7-git-send-email-Steven.Hill@imgtec.com>

Hello.

On 11/13/2014 9:05 AM, Steven J. Hill wrote:

> From: "Steven J. Hill" <Steven.Hill@imgtec.com>

> Add read/write macros to access the upper bits of the
> extended EntryLo0 and EntryLo1 registers used by XPA.

> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
>   arch/mips/include/asm/mipsregs.h |   39 ++++++++++++++++++++++++++++++++++++++
>   1 file changed, 39 insertions(+)

> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> index d767838..eaae8b0 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -997,6 +997,39 @@ do {									\
>   	local_irq_restore(__flags);					\
>   } while (0)
>
> +#define __readx_32bit_c0_register(source)				\
> +({									\
> +	unsigned int __res;						\
> +									\
> +	__asm__ __volatile__(						\
> +	"	.set	push					\n"	\
> +	"	.set	noat					\n"	\
> +	"	.set	mips32r2				\n"	\
> +	"	.insn						\n"	\
> +	"	# mfhc0 $1, %1					\n"	\
> +	"	.word	(0x40410000 | ((%1 & 0x1f) << 11))	\n"	\
> +	"	move	%0, $1					\n"	\
> +	"	.set	pop					\n"	\
> +	: "=r" (__res)							\
> +	: "i" (source));						\
> +	__res;								\
> +})
> +
> +#define __writex_32bit_c0_register(register, value)			\
> +do {									\
> +	__asm__ __volatile__(						\
> +	"	.set	push					\n"	\
> +	"	.set	noat					\n"	\
> +	"	.set	mips32r2				\n"	\
> +	"	move	$1, %0					\n"	\
> +	"	# mthc0 $1, %1					\n"	\
> +	"	.insn						\n"	\
> +	"	.word	(0x40c10000 | ((" #register " & 0x1f) << 11))	\n"	\

    Not %1 again?

> +	"	.set	pop					\n"	\
> +	:								\
> +	: "r" (value), "i" (register));					\
> +} while (0)
> +
[...]

WBR, Sergei

  reply	other threads:[~2014-11-13 12:25 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-13  6:05 [PATCH 00/11] Add support for eXtended Physical Addressing Steven J. Hill
2014-11-13  6:05 ` [PATCH 01/11] MIPS: HIGHMEM fixes for cache aliasing and non-DMA I/O Steven J. Hill
2014-11-13  6:05 ` [PATCH 02/11] MIPS: Revert fixrange_init() limiting to the FIXMAP region Steven J. Hill
2014-11-13 11:13   ` Ralf Baechle
2014-11-13  6:05 ` [PATCH 03/11] MIPS: Rearrange PTE bits into fixed positions for MIPS R2 Steven J. Hill
2014-11-13  6:05 ` [PATCH 04/11] MIPS: Removal of execute bit in page tables for HEAP/BSS Steven J. Hill
2014-11-13 11:36   ` Ralf Baechle
2014-11-13  6:05 ` [PATCH 05/11] MIPS: mm: c-r4k: Ensure CCA is set to non-coherent on UP kernels Steven J. Hill
2014-11-13 10:31   ` Ralf Baechle
2014-11-13  6:05 ` [PATCH 06/11] MIPS: Add CP0 macros for extended EntryLo registers Steven J. Hill
2014-11-13 12:25   ` Sergei Shtylyov [this message]
2014-11-13  6:05 ` [PATCH 07/11] MIPS: Fix address type used for early memory detection Steven J. Hill
2014-11-13  6:05 ` [PATCH 08/11] MIPS: Cosmetic cleanups of page table headers Steven J. Hill
2014-11-13  6:05 ` [PATCH 09/11] MIPS: Add MFHC0 and MTHC0 instructions to uasm Steven J. Hill
2014-11-13  6:05 ` [PATCH 10/11] MIPS: Add support for XPA Steven J. Hill
2014-11-13  6:05 ` [PATCH 11/11] MIPS: XPA: Add new configuration file Steven J. Hill
2014-11-13  6:21 ` [PATCH 00/11] Add support for eXtended Physical Addressing Ralf Baechle

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