Re: [PATCH V6 1/3] MIPS: Rearrange PTE bits into fixed positions.

[David Daney <ddaney.cavm@gmail.com>]

On 02/26/2015 11:01 AM, Steven J. Hill wrote:
> From: "Steven J. Hill" <Steven.Hill@imgtec.com>
>
> This patch rearranges the PTE bits into fixed positions for R2
> and later cores. In the past, the TLB handling code did runtime
> checking of RI/XI and adjusted the shifts and rotates in order
> to fit the largest PFN value into the PTE. The checking now
> occurs when building the TLB handler, thus eliminating those
> checks. These new arrangements also define the largest possible
> PFN value that can fit in the PTE. HUGE page support is only
> available on 64-bit platforms.
>
> The new layouts of the PTE bits are the following:
>
>     64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
>     32-bit, R1 or earler:      CCC D V G M A W R P
>     64-bit, R2 or later:       CCC D V G RI XI [S H] M A W R P
>     32-bit, R2 or later:       CCC D V G RI XI M A W R P
>
> In the case of cores that support the RI/XI bits, the value of
> the R bit is ignored.
>

Why not just use RI for everything, instead of taking up two bits to 
represent a single binary concept?

For the case where there is no RI hardware active, it is a purely 
software bit and you can easily invert the meaning and just have a 
_PAGE_NO_READ bit.

Also how does this change interact with __swp_type/_swp_offset/__swp_entry?

David Daney