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[85.141.197.124]) by mx.google.com with ESMTPSA id p3sm3679573lag.13.2015.04.19.06.51.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Apr 2015 06:51:59 -0700 (PDT) Message-ID: <5533B300.2050805@cogentembedded.com> Date: Sun, 19 Apr 2015 16:52:00 +0300 From: Sergei Shtylyov User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Alban Bedel , linux-mips@linux-mips.org CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Jason Cooper , Ralf Baechle , Andrew Bresticker , Qais Yousef , Gabor Juhos , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 03/12] devicetree: Add bindings for the ATH79 DDR controllers References: <1429448288-20742-1-git-send-email-albeu@free.fr> <1429448288-20742-4-git-send-email-albeu@free.fr> In-Reply-To: <1429448288-20742-4-git-send-email-albeu@free.fr> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 46934 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sergei.shtylyov@cogentembedded.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Hello. On 4/19/2015 3:57 PM, Alban Bedel wrote: > The DDR controller of the ARxxx and AR9xxx famillies provides an > interface to flush the FIFO between various devices and the DDR. > This is mainly used by the IRQ controller to flush the FIFO before > running the interrupt handler of such devices. > Signed-off-by: Alban Bedel > --- > v2: * Fix the node names to respect ePAPR I don't see where you did this. > --- > .../memory-controllers/ath79-ddr-controller.txt | 35 ++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt > new file mode 100644 > index 0000000..5541eed > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt > @@ -0,0 +1,35 @@ > +Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller > + > +The DDR controller of the ARxxx and AR9xxx famillies provides an interface Families. > +to flush the FIFO between various devices and the DDR. This is mainly used > +by the IRQ controller to flush the FIFO before running the interrupt handler > +of such devices. > + > +Required properties: > + > +- compatible: has to be "qca,-ddr-controller", > + "qca,[ar7100|ar7240]-ddr-controller" as fallback. > + On SoC with PCI support "qca,ar7100-ddr-controller" should be used as > + fallback, otherwise "qca,ar7240-ddr-controller" should be used. > +- reg: Base address and size of the controllers memory area > +- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer > + channel > + > +Example: > + > + ddr_ctrl: ddr-controller@18000000 { Should still be "memory-controller@18000000". > + compatible = "qca,ar9132-ddr-controller", > + "qca,ar7240-ddr-controller"; > + reg = <0x18000000 0x100>; > + > + #qca,ddr-wb-channel-cells = <1>; > + }; > + > + ... > + > + cpuintc@0 { "interrupt-controller" here? > + ... > + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; > + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, > + <&ddr_ctrl 0>, <&ddr_ctrl 1>; > + }; WBR, Sergei