From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 May 2016 04:50:31 +0200 (CEST) Received: from smtprelay4.synopsys.com ([198.182.47.9]:54020 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27006933AbcENCu1Ph4lK (ORCPT ); Sat, 14 May 2016 04:50:27 +0200 Received: from us02secmta1.synopsys.com (us02secmta1.synopsys.com [10.12.235.96]) by smtprelay.synopsys.com (Postfix) with ESMTP id 136E624E1585; Fri, 13 May 2016 19:50:18 -0700 (PDT) Received: from us02secmta1.internal.synopsys.com (us02secmta1.internal.synopsys.com [127.0.0.1]) by us02secmta1.internal.synopsys.com (Service) with ESMTP id A95A44E215; Fri, 13 May 2016 19:50:18 -0700 (PDT) Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by us02secmta1.internal.synopsys.com (Service) with ESMTP id 22A2C4E214; Fri, 13 May 2016 19:50:18 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 037E0EC2; Fri, 13 May 2016 19:50:18 -0700 (PDT) Received: from US01WEHTC2.internal.synopsys.com (us01wehtc2-vip.internal.synopsys.com [10.12.239.238]) by mailhost.synopsys.com (Postfix) with ESMTP id 65E29EBF; Fri, 13 May 2016 19:50:16 -0700 (PDT) Received: from US01WEHTC1.internal.synopsys.com (10.12.239.236) by US01WEHTC2.internal.synopsys.com (10.12.239.237) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 13 May 2016 19:50:16 -0700 Received: from [10.10.186.125] (10.10.186.125) by us01wehtc1.internal.synopsys.com (10.12.239.231) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 13 May 2016 19:50:15 -0700 Subject: Re: [PATCH v4] usb: dwc2: fix regression on big-endian PowerPC/ARM systems To: Arnd Bergmann , Christian Lamparter , Benjamin Herrenschmidt , Felipe Balbi References: <1463147559-544140-1-git-send-email-arnd@arndb.de> CC: "linux-mips@linux-mips.org" , "John.Youn@synopsys.com" , "gregkh@linuxfoundation.org" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "a.seppala@gmail.com" , "linuxppc-dev@lists.ozlabs.org" , Douglas Anderson , Gregory Herrero , Mian Yousaf Kaukab , Marek Szyprowski From: John Youn Message-ID: <57369267.6060308@synopsys.com> Date: Fri, 13 May 2016 19:50:15 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <1463147559-544140-1-git-send-email-arnd@arndb.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.10.186.125] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 53442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: John.Youn@synopsys.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 5/13/2016 6:53 AM, Arnd Bergmann wrote: > A patch that went into Linux-4.4 to fix big-endian mode on a Lantiq > MIPS system unfortunately broke big-endian operation on PowerPC > APM82181 as reported by Christian Lamparter, and likely other > systems. > > It actually introduced multiple issues: > > - it broke big-endian ARM kernels: any machine that was working > correctly with a little-endian kernel is no longer using byteswaps > on big-endian kernels, which clearly breaks them. > - On PowerPC the same thing must be true: if it was working before, > using big-endian kernels is now broken. Unlike ARM, 32-bit PowerPC > usually uses big-endian kernels, so they are likely all broken. > - The barrier for dwc2_writel is on the wrong side of the __raw_writel(), > so the MMIO no longer synchronizes with DMA operations. > - On architectures that require specific CPU instructions for MMIO > access, using the __raw_ variant may turn this into a pointer > dereference that does not have the same effect as the readl/writel. > > This patch is a simple revert for all architectures other than MIPS, > in the hope that we can more easily backport it to fix the regression > on PowerPC and ARM systems without breaking the Lantiq system again. > > We should follow this up with a more elaborate change to add runtime > detection of endianness, to make sure it also works on all other > combinations of architectures and implementations of the usb-dwc2 > device. That patch however will be fairly large and not appropriate > for backports to stable kernels. > > Felipe suggested a different approach, using an endianness switching > register to always put the device into LE mode, but unfortunately > the dwc2 hardware does not provide a generic way to do that. Also, > I see no practical way of addressing the problem more generally by > patching architecture specific code on MIPS. > > Signed-off-by: Arnd Bergmann > Fixes: 95c8bc360944 ("usb: dwc2: Use platform endianness when accessing registers") > --- > drivers/usb/dwc2/core.h | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h > index 3c58d633ce80..dec0b21fc626 100644 > --- a/drivers/usb/dwc2/core.h > +++ b/drivers/usb/dwc2/core.h > @@ -64,6 +64,17 @@ > DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ > dev_name(hsotg->dev), ##__VA_ARGS__) > > +#ifdef CONFIG_MIPS > +/* > + * There are some MIPS machines that can run in either big-endian > + * or little-endian mode and that use the dwc2 register without > + * a byteswap in both ways. > + * Unlike other architectures, MIPS apparently does not require a > + * barrier before the __raw_writel() to synchronize with DMA but does > + * require the barrier after the __raw_writel() to serialize a set of > + * writes. This set of operations was added specifically for MIPS and > + * should only be used there. > + */ > static inline u32 dwc2_readl(const void __iomem *addr) > { > u32 value = __raw_readl(addr); > @@ -90,6 +101,22 @@ static inline void dwc2_writel(u32 value, void __iomem *addr) > pr_info("INFO:: wrote %08x to %p\n", value, addr); > #endif > } > +#else > +/* Normal architectures just use readl/write */ > +static inline u32 dwc2_readl(const void __iomem *addr) > +{ > + return readl(addr); > +} > + > +static inline void dwc2_writel(u32 value, void __iomem *addr) > +{ > + writel(value, addr); > + > +#ifdef DWC2_LOG_WRITES > + pr_info("info:: wrote %08x to %p\n", value, addr); > +#endif > +} > +#endif > > /* Maximum number of Endpoints/HostChannels */ > #define MAX_EPS_CHANNELS 16 > Thanks Arnd. Acked-by: John Youn John