From: Paul Boddie <paul@boddie.org.uk>
To: Paul Cercueil <paul@crapouillou.net>
Cc: "H . Nikolaus Schaller" <hns@goldelico.com>,
周琰杰 <zhouyanjie@wanyeetech.com>,
linux-mips <linux-mips@vger.kernel.org>
Subject: Re: JZ4780 LCD controller initialisation (was Re: [PATCH] clocksource: Ingenic: Add high resolution timer support for SMP.)
Date: Wed, 27 May 2020 00:44:17 +0200 [thread overview]
Message-ID: <6095840.Tg7rQzGjE8@jeremy> (raw)
In-Reply-To: <4T1YAQ.877BANO14QDY2@crapouillou.net>
Paul,
Thanks for the reply!
On Tuesday 26. May 2020 17.03.04 Paul Cercueil wrote:
>
> "lcd0pixclk" and "tve" are for LCD0, "lcd1pixclk" and "lcd" are for
> LCD1.
The 3.0.8 kernel actually uses LCD0 for what the documentation and 3.18 kernel
call TVE, and it uses LCD1 for what the others call LCD. That earlier kernel
indicates that LCD1 is the parent clock of LCD0.
I actually found that you can enable LCD0 and not LCD1 and the LCD controller
(LCDC0) still operates to an extent, but without LCD1 enabled I didn't see a
DMA command value in the appropriate register, discussed below.
[...]
> OK, indeed the BPP and OSD config is read-only, and it's not a doc
> typo. How annoying.
>
> I tried to configure the LCD controller for a 8-byte descriptor without
> much success. No IRQs here either.
I had a look at the interrupt controller registers to see whether I was
missing anything obvious, but the mask was correctly configured to unmask LCD
interrupts (bit 31 of ICMR0). I did wonder whether the PDMA interrupts might
need unmasking, just in case there is some interaction between the peripherals
and that part of the hardware, but unmasking LCD interrupts there (bit 31 of
DMR0) didn't make any difference.
One observation I can make is that the length or size field of the LCD command
register (LCDCMD0) does get initialised to the appropriate value as set in a
descriptor. Since I don't set this register explicitly myself (unlike, I
think, the current Ingenic DRM driver in the Linux kernel), the value must
have been set up appropriately by a DMA transfer, as configured using the
descriptor address register (LCDDA0). However, the command flags I also set in
the descriptor are not reflected in the register. So, 0x44140000 becomes
0x00140000.
I thought I should check the interrupt ID register (LCDIID) to see what it
reveals. Despite setting a value in the appropriate descriptor field, the
register contains only zero.
I think I must probably tackle the job of initialising the HDMI controller to
see if that makes a difference. If the interrupts are not working but are also
not necessary, then maybe I get a visual indication of success.
Thanks for the feedback!
Paul
next prev parent reply other threads:[~2020-05-26 22:44 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 14:35 Introduce SMP support for CI20 (based on JZ4780) v8 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 0/6] Introduce SMP support for CI20 (based on JZ4780) 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support 周琰杰 (Zhou Yanjie)
2020-05-19 16:09 ` Paul Cercueil
2020-05-20 7:24 ` Zhou Yanjie
2020-05-19 18:21 ` kbuild test robot
2020-05-19 19:41 ` Paul Cercueil
2020-05-20 7:23 ` Zhou Yanjie
2020-05-20 11:33 ` Paul Cercueil
2020-05-20 12:32 ` Jiaxun Yang
2020-05-19 14:35 ` [PATCH v8 2/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 3/6] clocksource: Ingenic: Add high resolution timer support " 周琰杰 (Zhou Yanjie)
2020-05-19 17:42 ` Paul Cercueil
2020-05-19 20:11 ` [PATCH] " Paul Cercueil
2020-05-20 22:14 ` Paul Boddie
2020-05-22 12:26 ` Paul Cercueil
2020-05-22 19:16 ` Paul Boddie
2020-05-25 23:03 ` JZ4780 LCD controller initialisation (was Re: [PATCH] clocksource: Ingenic: Add high resolution timer support for SMP.) Paul Boddie
2020-05-26 4:48 ` H. Nikolaus Schaller
2020-05-26 15:03 ` Paul Cercueil
2020-05-26 22:44 ` Paul Boddie [this message]
2020-05-26 23:07 ` Paul Cercueil
2020-06-01 20:06 ` Paul Boddie
2020-06-23 21:28 ` Paul Boddie
2020-05-19 14:35 ` [PATCH v8 4/6] dt-bindings: MIPS: Document Ingenic SoCs binding 周琰杰 (Zhou Yanjie)
2020-05-26 19:29 ` Rob Herring
2020-05-27 5:59 ` Zhou Yanjie
2020-05-19 14:35 ` [PATCH v8 5/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-09-10 7:52 ` H. Nikolaus Schaller
2020-09-12 6:17 ` Zhou Yanjie
2020-05-19 14:35 ` [PATCH v8 6/6] MIPS: CI20: Update defconfig to support SMP 周琰杰 (Zhou Yanjie)
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