Linux MIPS Architecture development
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diff for duplicates of <72d10d33beedb9d877a7373dafc04a75@localhost>

diff --git a/a/content_digest b/N1/content_digest
index 4211cf5..cb84c86 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,8 +2,8 @@
  "Subject\0[PATCH 2/5] MIPS: sync after cacheflush\0"
  "Date\0Mon, 6 Sep 2010 21:03:46 -0700\0"
  "To\0Ralf Baechle <ralf@linux-mips.org>\0"
- "Cc\0<linux-mips@linux-mips.org>"
- " <linux-kernel@vger.kernel.org>\0"
+ "Cc\0linux-mips@linux-mips.org"
+ " linux-kernel@vger.kernel.org\0"
  "\00:1\0"
  "b\0"
  "On processors with deep write buffers, it is likely that many cycles\n"
@@ -74,4 +74,4 @@
  "-- \n"
  1.7.0.4
 
-de4accdb72ca44889504b7c8273f6b4a83a3113b1645c8df9cec6b0e2529bda9
+578d74e46a6b7eb369fc4fb5fc587068848d4bc73ef1414021abd3bd1d1fec2b

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