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Wed, 19 Jun 2024 07:33:26 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-522-ga39cca1d5-fm-20240610.002-ga39cca1d Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <859402a6-4e31-4029-a6ad-87c3be4d3fdd@app.fastmail.com> In-Reply-To: <20240616-mips-mt-fixes-v1-1-83913e0e60fc@flygoat.com> References: <20240616-mips-mt-fixes-v1-0-83913e0e60fc@flygoat.com> <20240616-mips-mt-fixes-v1-1-83913e0e60fc@flygoat.com> Date: Wed, 19 Jun 2024 12:32:50 +0100 From: "Jiaxun Yang" To: "Thomas Bogendoerfer" Cc: "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org, "stable@vger.kernel.org" Subject: Re: [PATCH fixes 1/4] MIPS: mipsmtregs: Fix target register for MFTC0 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B46=E6=9C=8816=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B=E5= =8D=882:25=EF=BC=8CJiaxun Yang=E5=86=99=E9=81=93=EF=BC=9A > Target register of mftc0 should be __res instead of $1, this is > a leftover from old .insn code. > > Fixes: dd6d29a61489 ("MIPS: Implement microMIPS MT ASE helpers") > Cc: stable@vger.kernel.org > Signed-off-by: Jiaxun Yang Hi Thomas, I saw you sent mips-fixes_6.10_1 pull request but this series is not included in that PR while one of my later patch is included. If you think the whole series is not fit for fixes tree then please at least let this series go through fixes tree. There are many MT users for routers etc and I don't want to risk break things for them in linus tree for too long. The patch itself is obvious. Thanks - Jiaxun > --- > arch/mips/include/asm/mipsmtregs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/mipsmtregs.h=20 > b/arch/mips/include/asm/mipsmtregs.h > index 30e86861c206..b1ee3c48e84b 100644 > --- a/arch/mips/include/asm/mipsmtregs.h > +++ b/arch/mips/include/asm/mipsmtregs.h > @@ -322,7 +322,7 @@ static inline void ehb(void) > " .set push \n" \ > " .set "MIPS_ISA_LEVEL" \n" \ > _ASM_SET_MFTC0 \ > - " mftc0 $1, " #rt ", " #sel " \n" \ > + " mftc0 %0, " #rt ", " #sel " \n" \ > _ASM_UNSET_MFTC0 \ > " .set pop \n" \ > : "=3Dr" (__res)); \ > > --=20 > 2.43.0 --=20 - Jiaxun