From: Thomas Gleixner <tglx@linutronix.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Florian Fainelli <florian.fainelli@broadcom.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>,
Huacai Chen <chenhuacai@kernel.org>,
Serge Semin <fancer.lancer@gmail.com>,
Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH v3 06/10] irqchip: irq-mips-gic: Switch to ipi_mux
Date: Fri, 23 Aug 2024 21:27:43 +0200 [thread overview]
Message-ID: <871q2fghu8.ffs@tglx> (raw)
In-Reply-To: <20240810-b4-mips-ipi-improvements-v3-6-1224fd7c4096@flygoat.com>
On Sat, Aug 10 2024 at 13:39, Jiaxun Yang wrote:
The interrupt subsystem uses irqchip/irq....: as prefix.
> Use ipi_mux to implement IPI interrupts instead of
> allocating vector for each individual IPI messages.
allocating separate vectors for ... IPI message.
> This can reduce number of reserved GIC shared vectors,
Can? Does it or does it not?
Also: the number
> which is a huge problem on MSI enabled GIC systems.
>
> It also allowed us to easily expand number of IPIs.
s/allowed us/allows/ the number
> int gic_get_c0_compare_int(void)
> {
> if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
> @@ -181,6 +176,11 @@ static void gic_mask_irq(struct irq_data *d)
> unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
>
> write_gic_rmask(intr);
> +
> +#ifdef CONFIG_GENERIC_IRQ_IPI
> + if (test_bit(intr, ipi_resrv))
> + return;
> +#endif
Can you please wrap this into a inline function so that you don't have
to sprinkle all these #ifdefs into the code?
#ifdef CONFIG_GENERIC_IRQ_IPI
static inline bool gic_is_reserved(unsigned int intr)
{
return test_bit(intr, ipi_resrv);
}
#else
static inline bool gic_is_reserved(unsigned int intr) { return false; }
#endif
Hmm?
> +static int gic_ipi_mux_init(struct device_node *node, struct irq_domain *d)
> {
> - struct irq_domain *gic_ipi_domain;
> - unsigned int v[2], num_ipis;
> -
> - gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
> - IRQ_DOMAIN_FLAG_IPI_PER_CPU,
> - GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
> - node, &gic_ipi_domain_ops, NULL);
> - if (!gic_ipi_domain) {
> - pr_err("Failed to add IPI domain");
> - return -ENXIO;
> - }
> -
> - irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
> + unsigned int i, v[2], num_ipis;
> + int ipi_virq, cpu = 0;
>
> if (node &&
> !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
Please use the full 100 characters width here and get rid of the line break.
> bitmap_set(ipi_resrv, v[0], v[1]);
> } else {
> /*
> - * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
> - * meeting the requirements of arch/mips SMP.
> + * Reserve 1 interrupts per possible CPU/VP for use as IPIs
> */
> - num_ipis = 2 * num_possible_cpus();
> + num_ipis = num_possible_cpus();
> bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
> }
Thanks,
tglx
next prev parent reply other threads:[~2024-08-23 19:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-10 12:39 [PATCH v3 00/10] MIPS: IPI Improvements Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 01/10] MIPS: smp: Make IPI interrupts scalable Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 02/10] MIPS: smp: Manage IPI interrupts as percpu_devid interrupts Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 03/10] MIPS: smp: Provide platform IPI virq & domain hooks Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 04/10] MIPS: Move mips_smp_ipi_init call after prepare_cpus Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 05/10] MIPS: smp: Implement IPI stats Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 06/10] irqchip: irq-mips-gic: Switch to ipi_mux Jiaxun Yang
2024-08-23 19:27 ` Thomas Gleixner [this message]
2024-08-10 12:39 ` [PATCH v3 07/10] MIPS: Implement get_mips_sw_int hook Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 08/10] MIPS: GIC: Implement get_sw_int hook Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 09/10] irqchip: irq-mips-cpu: Rework software IRQ handling flow Jiaxun Yang
2024-08-23 19:37 ` Thomas Gleixner
2024-08-24 9:52 ` Jiaxun Yang
2024-08-25 0:17 ` Thomas Gleixner
2024-08-10 12:39 ` [PATCH v3 10/10] MIPS: smp-mt: Rework IPI functions Jiaxun Yang
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