From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAD8BC433EF for ; Thu, 9 Jun 2022 16:44:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237756AbiFIQon (ORCPT ); Thu, 9 Jun 2022 12:44:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232459AbiFIQon (ORCPT ); Thu, 9 Jun 2022 12:44:43 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 054FC3EF15; Thu, 9 Jun 2022 09:44:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BE617B82D85; Thu, 9 Jun 2022 16:44:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BAC2C34114; Thu, 9 Jun 2022 16:44:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654793079; bh=XWTIu6xq2I66/SdQ0OlvXKQ/zKaWgtQgHLQd7mcVBIY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=flX894j3GgjAgV+X6ihLQ12oI1agwQCE1fAuTxoHFHV8P4rTRyUFba1Om5CxTA+j9 0+vRYynrrevyz+9M62JWZTt38qXC0dYiCioZFAlkQkEvmgyZ9rzDC/1xeuoVSDuutE Zc/OJn+Mx0NQwhP+xUmo99b7CNcorf3O8fQ+W07yKzV7AfzQCI+Jfw8up0vzm+hdXp gzrHj/c02h1sdp0/uJ2mV6GokiH4zrR6ddgIUxKJfDK2izgbz0QJyFFWBgpdZYT8ce wsPXBHwPXUk8NjPEFdP2zcwOcs0+KkpPx3VIr5eUCkrE3iF1tgYSfWsZTWdvbvXuPH e3w5Nqy/InjnA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nzLGu-00GvvR-NS; Thu, 09 Jun 2022 17:44:36 +0100 Date: Thu, 09 Jun 2022 17:44:36 +0100 Message-ID: <877d5p4wi3.wl-maz@kernel.org> From: Marc Zyngier To: Jiaxun Yang Cc: Huacai Chen , WANG Xuerui , LKML , "open list:MIPS" Subject: Re: [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid In-Reply-To: <01dd74cb-b53c-93e3-d27f-57603d348f67@flygoat.com> References: <20220604124052.1550-1-jiaxun.yang@flygoat.com> <01dd74cb-b53c-93e3-d27f-57603d348f67@flygoat.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jiaxun.yang@flygoat.com, chenhuacai@kernel.org, kernel@xen0n.name, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Sat, 04 Jun 2022 14:46:30 +0100, Jiaxun Yang wrote: >=20 >=20 >=20 > =E5=9C=A8 2022/6/4 14:18, Huacai Chen =E5=86=99=E9=81=93: > > Hi, Jiaxun, > >=20 > > On Sat, Jun 4, 2022 at 8:41 PM Jiaxun Yang wr= ote: > >> fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for > >> LoongArch") replaced get_ebase_cpunum with physical processor > >> id from SMP facilities. However that breaks MIPS non-SMP build > >> and makes booting from other cores inpossible on non-SMP kernel. > >>=20 > >> Thus we revert get_ebase_cpunum back and use get_csr_cpuid for > >> LoongArch. > >>=20 > >> Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for Lo= ongArch") > >> Signed-off-by: Jiaxun Yang > >> --- > >> drivers/irqchip/irq-loongson-liointc.c | 10 +++++++++- > >> 1 file changed, 9 insertions(+), 1 deletion(-) > >>=20 > >> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/= irq-loongson-liointc.c > >> index aed88857d90f..c11cf97bcd1a 100644 > >> --- a/drivers/irqchip/irq-loongson-liointc.c > >> +++ b/drivers/irqchip/irq-loongson-liointc.c > >> @@ -39,6 +39,14 @@ > >>=20 > >> #define LIOINTC_ERRATA_IRQ 10 > >>=20 > >> +#if defined(CONFIG_MIPS) > >> +#define liointc_core_id get_ebase_cpunum() > >> +#elif defined(CONFIG_LOONGARCH) > >> +#define liointc_core_id get_csr_cpuid() > >> +#else > >> +#define liointc_core_id 0 > >> +#endif > > Thank you for your quick fix. But I think it is better to do like this: > >=20 > > #if defined(CONFIG_LOONGARCH) > > #define liointc_core_id get_csr_cpuid() > > #else > > #define liointc_core_id get_ebase_cpunum() > > #endif > >=20 > > Because this driver doesn't depend on COMPILE_TEST, it can only be > > built under MIPS and LOONGARCH. Moreover, let the else branch be the > > same as the old behavior looks more reasonable. > Thanks for the suggestion. > Will do for v2. Any update on this? I believe MIPS is still broken. Thanks, M. --=20 Without deviation from the norm, progress is not possible.