* [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid
@ 2022-06-04 12:40 Jiaxun Yang
2022-06-04 12:40 ` [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid Jiaxun Yang
2022-06-04 13:18 ` [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Huacai Chen
0 siblings, 2 replies; 6+ messages in thread
From: Jiaxun Yang @ 2022-06-04 12:40 UTC (permalink / raw)
To: chenhuacai; +Cc: kernel, maz, linux-kernel, linux-mips, Jiaxun Yang
fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.
Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.
Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
drivers/irqchip/irq-loongson-liointc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index aed88857d90f..c11cf97bcd1a 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -39,6 +39,14 @@
#define LIOINTC_ERRATA_IRQ 10
+#if defined(CONFIG_MIPS)
+#define liointc_core_id get_ebase_cpunum()
+#elif defined(CONFIG_LOONGARCH)
+#define liointc_core_id get_csr_cpuid()
+#else
+#define liointc_core_id 0
+#endif
+
struct liointc_handler_data {
struct liointc_priv *priv;
u32 parent_int_map;
@@ -57,7 +65,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_chip_generic *gc = handler->priv->gc;
- int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
+ int core = liointc_core_id % LIOINTC_NUM_CORES;
u32 pending;
chained_irq_enter(chip, desc);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid
2022-06-04 12:40 [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Jiaxun Yang
@ 2022-06-04 12:40 ` Jiaxun Yang
2022-06-04 13:11 ` Huacai Chen
2022-06-04 13:18 ` [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Huacai Chen
1 sibling, 1 reply; 6+ messages in thread
From: Jiaxun Yang @ 2022-06-04 12:40 UTC (permalink / raw)
To: chenhuacai; +Cc: kernel, maz, linux-kernel, linux-mips, Jiaxun Yang
Only low 9 bits of CPUID CSR represents coreid, higher bits
are marked as reserved. In case Loongson may define higher
bits in future, just mask them out for get_csr_cpuid.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/loongarch/include/asm/loongarch.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 3ba4f7e87cd2..7f3933f747f9 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1200,7 +1200,7 @@ static inline u64 drdtime(void)
static inline unsigned int get_csr_cpuid(void)
{
- return csr_read32(LOONGARCH_CSR_CPUID);
+ return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
}
static inline void csr_any_send(unsigned int addr, unsigned int data,
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid
2022-06-04 12:40 ` [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid Jiaxun Yang
@ 2022-06-04 13:11 ` Huacai Chen
0 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2022-06-04 13:11 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: WANG Xuerui, Marc Zyngier, LKML, open list:MIPS
Hi, Jiaxun,
On Sat, Jun 4, 2022 at 8:41 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> Only low 9 bits of CPUID CSR represents coreid, higher bits
> are marked as reserved. In case Loongson may define higher
> bits in future, just mask them out for get_csr_cpuid.
I think we needn't to modify, until the high bits actually get defined. :)
Huacai
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> arch/loongarch/include/asm/loongarch.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 3ba4f7e87cd2..7f3933f747f9 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -1200,7 +1200,7 @@ static inline u64 drdtime(void)
>
> static inline unsigned int get_csr_cpuid(void)
> {
> - return csr_read32(LOONGARCH_CSR_CPUID);
> + return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
> }
>
> static inline void csr_any_send(unsigned int addr, unsigned int data,
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid
2022-06-04 12:40 [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Jiaxun Yang
2022-06-04 12:40 ` [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid Jiaxun Yang
@ 2022-06-04 13:18 ` Huacai Chen
2022-06-04 13:46 ` Jiaxun Yang
1 sibling, 1 reply; 6+ messages in thread
From: Huacai Chen @ 2022-06-04 13:18 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: WANG Xuerui, Marc Zyngier, LKML, open list:MIPS
Hi, Jiaxun,
On Sat, Jun 4, 2022 at 8:41 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
> LoongArch") replaced get_ebase_cpunum with physical processor
> id from SMP facilities. However that breaks MIPS non-SMP build
> and makes booting from other cores inpossible on non-SMP kernel.
>
> Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
> LoongArch.
>
> Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> drivers/irqchip/irq-loongson-liointc.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index aed88857d90f..c11cf97bcd1a 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -39,6 +39,14 @@
>
> #define LIOINTC_ERRATA_IRQ 10
>
> +#if defined(CONFIG_MIPS)
> +#define liointc_core_id get_ebase_cpunum()
> +#elif defined(CONFIG_LOONGARCH)
> +#define liointc_core_id get_csr_cpuid()
> +#else
> +#define liointc_core_id 0
> +#endif
Thank you for your quick fix. But I think it is better to do like this:
#if defined(CONFIG_LOONGARCH)
#define liointc_core_id get_csr_cpuid()
#else
#define liointc_core_id get_ebase_cpunum()
#endif
Because this driver doesn't depend on COMPILE_TEST, it can only be
built under MIPS and LOONGARCH. Moreover, let the else branch be the
same as the old behavior looks more reasonable.
Huacai
> +
> struct liointc_handler_data {
> struct liointc_priv *priv;
> u32 parent_int_map;
> @@ -57,7 +65,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
> struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct irq_chip_generic *gc = handler->priv->gc;
> - int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
> + int core = liointc_core_id % LIOINTC_NUM_CORES;
> u32 pending;
>
> chained_irq_enter(chip, desc);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid
2022-06-04 13:18 ` [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Huacai Chen
@ 2022-06-04 13:46 ` Jiaxun Yang
2022-06-09 16:44 ` Marc Zyngier
0 siblings, 1 reply; 6+ messages in thread
From: Jiaxun Yang @ 2022-06-04 13:46 UTC (permalink / raw)
To: Huacai Chen; +Cc: WANG Xuerui, Marc Zyngier, LKML, open list:MIPS
在 2022/6/4 14:18, Huacai Chen 写道:
> Hi, Jiaxun,
>
> On Sat, Jun 4, 2022 at 8:41 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
>> LoongArch") replaced get_ebase_cpunum with physical processor
>> id from SMP facilities. However that breaks MIPS non-SMP build
>> and makes booting from other cores inpossible on non-SMP kernel.
>>
>> Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
>> LoongArch.
>>
>> Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> drivers/irqchip/irq-loongson-liointc.c | 10 +++++++++-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
>> index aed88857d90f..c11cf97bcd1a 100644
>> --- a/drivers/irqchip/irq-loongson-liointc.c
>> +++ b/drivers/irqchip/irq-loongson-liointc.c
>> @@ -39,6 +39,14 @@
>>
>> #define LIOINTC_ERRATA_IRQ 10
>>
>> +#if defined(CONFIG_MIPS)
>> +#define liointc_core_id get_ebase_cpunum()
>> +#elif defined(CONFIG_LOONGARCH)
>> +#define liointc_core_id get_csr_cpuid()
>> +#else
>> +#define liointc_core_id 0
>> +#endif
> Thank you for your quick fix. But I think it is better to do like this:
>
> #if defined(CONFIG_LOONGARCH)
> #define liointc_core_id get_csr_cpuid()
> #else
> #define liointc_core_id get_ebase_cpunum()
> #endif
>
> Because this driver doesn't depend on COMPILE_TEST, it can only be
> built under MIPS and LOONGARCH. Moreover, let the else branch be the
> same as the old behavior looks more reasonable.
Thanks for the suggestion.
Will do for v2.
- Jiaxun
>
> Huacai
>
>> +
>> struct liointc_handler_data {
>> struct liointc_priv *priv;
>> u32 parent_int_map;
>> @@ -57,7 +65,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
>> struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
>> struct irq_chip *chip = irq_desc_get_chip(desc);
>> struct irq_chip_generic *gc = handler->priv->gc;
>> - int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
>> + int core = liointc_core_id % LIOINTC_NUM_CORES;
>> u32 pending;
>>
>> chained_irq_enter(chip, desc);
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid
2022-06-04 13:46 ` Jiaxun Yang
@ 2022-06-09 16:44 ` Marc Zyngier
0 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2022-06-09 16:44 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: Huacai Chen, WANG Xuerui, LKML, open list:MIPS
On Sat, 04 Jun 2022 14:46:30 +0100,
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
>
>
> 在 2022/6/4 14:18, Huacai Chen 写道:
> > Hi, Jiaxun,
> >
> > On Sat, Jun 4, 2022 at 8:41 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >> fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
> >> LoongArch") replaced get_ebase_cpunum with physical processor
> >> id from SMP facilities. However that breaks MIPS non-SMP build
> >> and makes booting from other cores inpossible on non-SMP kernel.
> >>
> >> Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
> >> LoongArch.
> >>
> >> Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >> ---
> >> drivers/irqchip/irq-loongson-liointc.c | 10 +++++++++-
> >> 1 file changed, 9 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> >> index aed88857d90f..c11cf97bcd1a 100644
> >> --- a/drivers/irqchip/irq-loongson-liointc.c
> >> +++ b/drivers/irqchip/irq-loongson-liointc.c
> >> @@ -39,6 +39,14 @@
> >>
> >> #define LIOINTC_ERRATA_IRQ 10
> >>
> >> +#if defined(CONFIG_MIPS)
> >> +#define liointc_core_id get_ebase_cpunum()
> >> +#elif defined(CONFIG_LOONGARCH)
> >> +#define liointc_core_id get_csr_cpuid()
> >> +#else
> >> +#define liointc_core_id 0
> >> +#endif
> > Thank you for your quick fix. But I think it is better to do like this:
> >
> > #if defined(CONFIG_LOONGARCH)
> > #define liointc_core_id get_csr_cpuid()
> > #else
> > #define liointc_core_id get_ebase_cpunum()
> > #endif
> >
> > Because this driver doesn't depend on COMPILE_TEST, it can only be
> > built under MIPS and LOONGARCH. Moreover, let the else branch be the
> > same as the old behavior looks more reasonable.
> Thanks for the suggestion.
> Will do for v2.
Any update on this? I believe MIPS is still broken.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-06-09 16:44 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2022-06-04 12:40 [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Jiaxun Yang
2022-06-04 12:40 ` [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid Jiaxun Yang
2022-06-04 13:11 ` Huacai Chen
2022-06-04 13:18 ` [PATCH for-5.19 1/2] irqchip/loongson-liointc: Use architecture register to get coreid Huacai Chen
2022-06-04 13:46 ` Jiaxun Yang
2022-06-09 16:44 ` Marc Zyngier
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