From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7712C43334 for ; Wed, 6 Jul 2022 09:54:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232403AbiGFJyt (ORCPT ); Wed, 6 Jul 2022 05:54:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232165AbiGFJx7 (ORCPT ); Wed, 6 Jul 2022 05:53:59 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A41B424BE8; Wed, 6 Jul 2022 02:53:39 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 34B6E61D40; Wed, 6 Jul 2022 09:53:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82572C3411C; Wed, 6 Jul 2022 09:53:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657101218; bh=1+TAW3exq0FTcdqhQcZKOa7G8b91AXQ62ylYG4tiE1s=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=XZzdP/nE43npYcuU5VLFWOLEu7CAY2xradQzsG53GYYZD4Z1yATQHp7+ZwH7Hmq3e W+oAqxiFLivWkHzeB3SrUROrHF5SpM6jC46XBBkwvwFYowh73cYe2E4MbbCv7phQRA x7Os2L8LYJvB3MfqpNQ7XLbonvqc1qs/8Ku/V7BbQC5BKPLw2n1e4UD4Mb7PXR4iOW byx/YElAuTAFKamDd+nYUQJiYgnF9Qq5ZaBO6Zk0XK4wSLSs6pL3m99jRuCn2pHUST os1Nipx1oaQSeFLP1Eh5WwPQns2LoEglu5+t4HClMojsezlNRz9XaAn+A7xaeQ92aE Au6lEIOEQAfxw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o91iy-005aui-Bc; Wed, 06 Jul 2022 10:53:36 +0100 Date: Wed, 06 Jul 2022 10:53:36 +0100 Message-ID: <87h73u1s9r.wl-maz@kernel.org> From: Marc Zyngier To: Thomas Bogendoerfer Cc: Sander Vanheule , Aleksander Jan Bajkowski , martin.blumenstingl@googlemail.com, hauke@hauke-m.de, git@birger-koblitz.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE In-Reply-To: <20220706081901.GA10797@alpha.franken.de> References: <20220702190705.5319-1-olek2@wp.pl> <3c9a032edd0fb9b9608ad3ca08d6e3cc38f21464.camel@svanheule.net> <87fsjen2kl.wl-maz@kernel.org> <20220706081901.GA10797@alpha.franken.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tsbogend@alpha.franken.de, sander@svanheule.net, olek2@wp.pl, martin.blumenstingl@googlemail.com, hauke@hauke-m.de, git@birger-koblitz.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Wed, 06 Jul 2022 09:19:01 +0100, Thomas Bogendoerfer wrote: > > On Wed, Jul 06, 2022 at 08:05:30AM +0100, Marc Zyngier wrote: > > On Sun, 03 Jul 2022 19:15:11 +0100, > > Sander Vanheule wrote: > > > > > > Hi Aleksander, > > > > > > Since this is IRQ related: +CC Marc Zyngier > > > > > > On Sat, 2022-07-02 at 21:07 +0200, Aleksander Jan Bajkowski wrote: > > > > This patch is needed to handle interrupts by the second VPE on > > > > the Lantiq xRX200, xRX300 and xRX330 SoCs. In these chips, 32 ICU > > > > interrupts are connected to each hardware line. The SoC supports > > > > a total of 160 interrupts. Currently changing smp_affinity to the > > > > second VPE hangs interrupts. > > > > > > > > This problem affects multithreaded SoCs with a custom interrupt > > > > controller. Chips with 1004Kc core and newer use the MIPS GIC. > > > > > > > > Also CC'ed Birger Koblitz and Sander Vanheule. Both are working > > > > on support for Realtek RTL930x chips with 34Kc core and Birger > > > > has added a patch in OpenWRT that also enables all interrupt > > > > lines. So it looks like this patch is useful for more SoCs. > > > > > > > > Tested on lantiq xRX200 and xRX330. > > > > > > > > Signed-off-by: Aleksander Jan Bajkowski > > > > > > Thanks for bringing up this issue. Like you say OpenWrt carries a > > > similar patch, and I also carry a patch on my tree to enable all CPU > > > IRQ lines. > > > > > > Indiscriminately enabling all IRQ lines doesn't sit quite right with > > > me though, since I would expect these to be enabled > > > on-demand. I.e. when a peripheral requests an IRQ, or when an IRQ > > > controller is cascaded into one of the CPU's interrupt lines. If I > > > understand correctly, the IRQ mask/unmask functions in > > > drivers/irqchip/irq-mips-cpu.c should do this. > > > > But this is only enabling interrupts at the CPU level, right? And the > > irqchip is still in control of the masking of the individual > > interrupts? > > in the Lantiq case yes > > > If both assertions are true, then this patch seems OK. If it just let > > any interrupt through without any control, then this is wrong. > > > > So which one is it? > > if there isn't an additional irqchip connected to the cpu interrupt lines, > this patch will cause problems. And that's what the irq-mips-cpu driver should solve, right? In this case, what's the problem with adopting this driver for the Lantiq platform (and all other ones using the same CPU)? M. -- Without deviation from the norm, progress is not possible.