From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E45ED36AE9; Sat, 10 Feb 2024 09:32:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707557545; cv=none; b=g2VQ/NUfgBzeQcvxABXCeF4BRE6vGQIv6wnNAVmA4pLAyzBnTszar4AE+etyNZ9gq9H4bSdzLJ1HSAVLMPUTEiPYeV2h2ZfTzMeJgudyirAIoE89K/5jtU59XmMcV9rxKoqFf5mdQlryDfhkXkexz5NTodfKgkQNzL5Id/j5NGo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707557545; c=relaxed/simple; bh=zmgXIy+KvUSnQwp4jEHGf3DonxJlpcSWYSJAEKZmDWI=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Oe3UKsR7iQSceWlUbB0Wb/+16fdvgvx0FdDLt30fGZ01h4+mmkiDwanHkq45KXGlHBRJsunLm+KhQQ95lQriSM12yuIHajws2mG3iozBayKrAns0N/FBeI8BvCFZNXobil/7XRO23Uh886+OJJxVC92Rs/3wut40HyPOP6OdBF4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HvSGhUUy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HvSGhUUy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41DCBC433C7; Sat, 10 Feb 2024 09:32:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707557544; bh=zmgXIy+KvUSnQwp4jEHGf3DonxJlpcSWYSJAEKZmDWI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=HvSGhUUyyOuBRuCXxIoQiRxNoGp+6rDitXgJrQG81NV4mn7ggzBfJLY2TPj4JWiVz nvSqSJD2FqqRMgzNSLs14Xo7ylk0x6MC/TGgnSMzs23XqzFJQZfsBBQDaIyUsWMcJ3 4iEFQRh6wddLUtKVY3uul1yS10B3pmLa/A1p439r390qSdN4235FEhIT4S0wPluzYk FtbAjyMef07KwZi5fNe9n3H3LzXdysuH2O7pIZ1V35MbnnWEsENrXozdmF8CGdXykr SZRLk6dmfkfT5itX4jJCoRRbJAifTRRh04ffoRR0Xg/ntr3UjkzcbRGGY+Oe2CnWWa BNrfMfLT2rwrQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rYjif-001yPz-Gb; Sat, 10 Feb 2024 09:32:21 +0000 Date: Sat, 10 Feb 2024 09:32:21 +0000 Message-ID: <87jzncwtp6.wl-maz@kernel.org> From: Marc Zyngier To: Florian Fainelli Cc: linux-kernel@vger.kernel.org, Doug Berger , Broadcom internal kernel review list , Thomas Gleixner , Brian Norris , Jason Cooper , linux-mips@vger.kernel.org (open list:BROADCOM BMIPS MIPS ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: Re: [PATCH v2] irqchip/irq-brcmstb-l2: add write memory barrier before exit In-Reply-To: <20240210012449.3009125-1-florian.fainelli@broadcom.com> References: <20240210012449.3009125-1-florian.fainelli@broadcom.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: florian.fainelli@broadcom.com, linux-kernel@vger.kernel.org, opendmb@gmail.com, bcm-kernel-feedback-list@broadcom.com, tglx@linutronix.de, computersforpeace@gmail.com, jason@lakedaemon.net, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 10 Feb 2024 01:24:49 +0000, Florian Fainelli wrote: > > From: Doug Berger > > It was observed on Broadcom devices that use GIC v3 architecture > L1 interrupt controllers as the parent of brcmstb-l2 interrupt > controllers that the deactivation of the parent irq could happen > before the brcmstb-l2 deasserted its output. This would lead the > GIC to reactivate the irq only to find that no L2 interrupt was > pending. The result was a spurious interrupt invoking the > handle_bad_irq() with its associated messaging. While this did > not create a functional problem it is a waste of cycles. > > The hazard exists because the memory mapped bus writes to the > brcmstb-l2 registers are buffered and the GIC v3 architecture > uses a very efficient system register write to deactivate the > interrupt. This commit adds a write memory barrier prior to > invoking chained_irq_exit() to introduce a dsb(st) on those > systems to ensure the system register write cannot be executed > until the memory mapped writes are visible to the system. > > Signed-off-by: Doug Berger > Acked-by: Florian Fainelli > Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller") > [florian: Added Fixes tag] > Signed-off-by: Florian Fainelli Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.