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From: Marc Zyngier <maz@kernel.org>
To: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Chao-ying Fu <cfu@wavecomp.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Greg Ungerer <gerg@kernel.org>, Hauke Mehrtens <hauke@hauke-m.de>,
	Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
	Paul Burton <paulburton@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Serge Semin <fancer.lancer@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Tiezhu Yang <yangtiezhu@loongson.cn>,
	Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Subject: Re: [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu()
Date: Mon, 06 Jun 2022 14:05:37 +0100	[thread overview]
Message-ID: <87v8te3psu.wl-maz@kernel.org> (raw)
In-Reply-To: <20220525121030.16054-4-Dragan.Mladjenovic@syrmia.com>

On Wed, 25 May 2022 13:10:21 +0100,
Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com> wrote:
> 
> From: Paul Burton <paulburton@kernel.org>
> 
> A few pieces of code in the MIPS GIC driver operate on the GIC local
> register block for each online CPU, accessing each via the GIC's
> other/redirect register block. This patch abstracts the process of
> iterating over online CPUs & configuring the other/redirect region to
> access their registers through a new gic_with_each_online_cpu() macro.
> 
> This simplifies users of the new macro slightly, and more importantly
> prepares us for handling multi-cluster systems where the register
> configuration will be done via the CM's GCR_CL_REDIRECT register. By
> abstracting all other/redirect block configuration through this macro,
> and the __gic_with_next_online_cpu() function which backs it, users will
> trivially gain support for multi-cluster when it is implemented in
> __gic_with_next_online_cpu().
> 
> Signed-off-by: Paul Burton <paulburton@kernel.org>
> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
> 
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index ff89b36267dd..4872bebe24cf 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -65,6 +65,45 @@ static struct gic_all_vpes_chip_data {
>  	bool	mask;
>  } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
>  
> +static int __gic_with_next_online_cpu(int prev)
> +{
> +	unsigned int cpu;
> +
> +	/* Discover the next online CPU */
> +	cpu = cpumask_next(prev, cpu_online_mask);
> +
> +	/* If there isn't one, we're done */
> +	if (cpu >= nr_cpu_ids)
> +		return cpu;
> +
> +	/*
> +	 * Lock access to the next CPU's GIC local register block.
> +	 *
> +	 * In the single cluster case we simply set GIC_VL_OTHER. The caller
> +	 * holds gic_lock so nothing can clobber the value we write.
> +	 */
> +	write_gic_vl_other(mips_cm_vp_id(cpu));
> +
> +	return cpu;
> +}
> +
> +/**
> + * gic_with_each_online_cpu() - Iterate over online CPUs, access local registers
> + * @cpu: An integer variable to hold the current CPU number
> + *
> + * Iterate over online CPUs & configure the other/redirect register region to
> + * access each CPUs GIC local register block, which can be accessed from the
> + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or
> + * their derivatives.
> + *
> + * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER
> + * cannot be clobbered.
> + */
> +#define gic_with_each_online_cpu(cpu)			\

nit: please keep the kernel convention of using 'for_each'. This makes
it far easier to grep for such iterators when doing bulk refactoring.

Also, since there is a requirement to hold the gic_lock, please add a
lockdep_assert_held() in the loop so that it can be checked with a
lockdep kernel.

> +	for ((cpu) = __gic_with_next_online_cpu(-1);	\
> +	     (cpu) = __gic_with_next_online_cpu(cpu),	\
> +	     (cpu) < nr_cpu_ids;)
> +
>  static void gic_clear_pcpu_masks(unsigned int intr)
>  {
>  	unsigned int i;
> @@ -357,10 +396,8 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
>  	cd->mask = false;
>  
>  	spin_lock_irqsave(&gic_lock, flags);
> -	for_each_online_cpu(cpu) {
> -		write_gic_vl_other(mips_cm_vp_id(cpu));
> +	gic_with_each_online_cpu(cpu)
>  		write_gic_vo_rmask(BIT(intr));
> -	}
>  	spin_unlock_irqrestore(&gic_lock, flags);
>  }
>  
> @@ -375,10 +412,8 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
>  	cd->mask = true;
>  
>  	spin_lock_irqsave(&gic_lock, flags);
> -	for_each_online_cpu(cpu) {
> -		write_gic_vl_other(mips_cm_vp_id(cpu));
> +	gic_with_each_online_cpu(cpu)
>  		write_gic_vo_smask(BIT(intr));
> -	}
>  	spin_unlock_irqrestore(&gic_lock, flags);
>  }
>  
> @@ -532,10 +567,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
>  		return -EPERM;
>  
>  	spin_lock_irqsave(&gic_lock, flags);
> -	for_each_online_cpu(cpu) {
> -		write_gic_vl_other(mips_cm_vp_id(cpu));
> +	gic_with_each_online_cpu(cpu)
>  		write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
> -	}
>  	spin_unlock_irqrestore(&gic_lock, flags);
>  
>  	return 0;

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2022-06-06 13:05 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-25 12:10 [PATCH v2 00/12] MIPS: Support I6500 multi-cluster configuration Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 01/12] MIPS: CPS: Add a couple of multi-cluster utility functions Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 02/12] MIPS: GIC: Generate redirect block accessors Dragan Mladjenovic
2022-05-25 18:33   ` Jiaxun Yang
2022-05-25 12:10 ` [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() Dragan Mladjenovic
2022-06-06 13:05   ` Marc Zyngier [this message]
2022-05-25 12:10 ` [PATCH v2 04/12] irqchip: mips-gic: Support multi-cluster in gic_with_each_online_cpu() Dragan Mladjenovic
2022-06-06 13:13   ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 05/12] irqchip: mips-gic: Setup defaults in each cluster Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support Dragan Mladjenovic
2022-06-06 11:47   ` Marc Zyngier
2022-06-07 18:23     ` Jiaxun Yang
2022-06-08  6:05       ` Marc Zyngier
2022-06-09 10:14         ` Jiaxun Yang
2022-06-09 11:54           ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 07/12] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Dragan Mladjenovic
2022-06-27 14:17   ` Dragan Mladjenovic
2022-06-27 14:27     ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 08/12] clocksource: mips-gic-timer: Enable counter when CPUs start Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 09/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 10/12] MIPS: CPS: Introduce struct cluster_boot_config Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 11/12] MIPS: Report cluster in /proc/cpuinfo Dragan Mladjenovic
2022-06-06 13:14   ` Marc Zyngier
2022-06-07 18:27     ` Jiaxun Yang
2022-06-08  6:13       ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 12/12] MIPS: CPS: Boot CPUs in secondary clusters Dragan Mladjenovic

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