From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B306BC433EF for ; Mon, 6 Jun 2022 13:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238280AbiFFNFr (ORCPT ); Mon, 6 Jun 2022 09:05:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238264AbiFFNFp (ORCPT ); Mon, 6 Jun 2022 09:05:45 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C2EE38D90; Mon, 6 Jun 2022 06:05:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 7A5F2CE1A8F; Mon, 6 Jun 2022 13:05:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3A26C3411F; Mon, 6 Jun 2022 13:05:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654520739; bh=xtSZpREwcefu3/OKJIzEr4wdqXfHclweHI5c8Rpk0R0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=a+8qy0zJAIbbXlHJQMfbAdDlms89dwtXgyg0bQ0WaLy+yPPTYrknJhqrKo88VMfTR d3I/tYtVVKDAcwZf+cHTgafy0QLm4ofSC1n8KucjFoFf6eWFy2Eu12Pvzx0qlobPfS Euy298/3+/p2pR/NHTkwx9B9M8ihQjsNrIkb6yArJ91uMzST0pPVXpjvGsuRncs99C fSIso33/WkUdJpkLtJ65RITU0EySxz6hvIKPUmvlEWj8go0KJCGypFW4botcKAr4S2 D+zwQb2UEjWqs5yZ7UdBDjsoXDypRw2x+tHXpezvKA/3DSWLB4Ev59cwKLkOlOSLQ0 4IEZVi2nuZh5w== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nyCQL-00FuCO-Ek; Mon, 06 Jun 2022 14:05:37 +0100 Date: Mon, 06 Jun 2022 14:05:37 +0100 Message-ID: <87v8te3psu.wl-maz@kernel.org> From: Marc Zyngier To: Dragan Mladjenovic Cc: Thomas Bogendoerfer , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: Re: [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() In-Reply-To: <20220525121030.16054-4-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> <20220525121030.16054-4-Dragan.Mladjenovic@syrmia.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Dragan.Mladjenovic@syrmia.com, tsbogend@alpha.franken.de, cfu@wavecomp.com, daniel.lezcano@linaro.org, geert@linux-m68k.org, gerg@kernel.org, hauke@hauke-m.de, ilya.lipnitskiy@gmail.com, jiaxun.yang@flygoat.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, paulburton@kernel.org, peterz@infradead.org, fancer.lancer@gmail.com, tglx@linutronix.de, yangtiezhu@loongson.cn, dragan.mladjenovic@syrmia.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Wed, 25 May 2022 13:10:21 +0100, Dragan Mladjenovic wrote: > > From: Paul Burton > > A few pieces of code in the MIPS GIC driver operate on the GIC local > register block for each online CPU, accessing each via the GIC's > other/redirect register block. This patch abstracts the process of > iterating over online CPUs & configuring the other/redirect region to > access their registers through a new gic_with_each_online_cpu() macro. > > This simplifies users of the new macro slightly, and more importantly > prepares us for handling multi-cluster systems where the register > configuration will be done via the CM's GCR_CL_REDIRECT register. By > abstracting all other/redirect block configuration through this macro, > and the __gic_with_next_online_cpu() function which backs it, users will > trivially gain support for multi-cluster when it is implemented in > __gic_with_next_online_cpu(). > > Signed-off-by: Paul Burton > Signed-off-by: Chao-ying Fu > Signed-off-by: Dragan Mladjenovic > > diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c > index ff89b36267dd..4872bebe24cf 100644 > --- a/drivers/irqchip/irq-mips-gic.c > +++ b/drivers/irqchip/irq-mips-gic.c > @@ -65,6 +65,45 @@ static struct gic_all_vpes_chip_data { > bool mask; > } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; > > +static int __gic_with_next_online_cpu(int prev) > +{ > + unsigned int cpu; > + > + /* Discover the next online CPU */ > + cpu = cpumask_next(prev, cpu_online_mask); > + > + /* If there isn't one, we're done */ > + if (cpu >= nr_cpu_ids) > + return cpu; > + > + /* > + * Lock access to the next CPU's GIC local register block. > + * > + * In the single cluster case we simply set GIC_VL_OTHER. The caller > + * holds gic_lock so nothing can clobber the value we write. > + */ > + write_gic_vl_other(mips_cm_vp_id(cpu)); > + > + return cpu; > +} > + > +/** > + * gic_with_each_online_cpu() - Iterate over online CPUs, access local registers > + * @cpu: An integer variable to hold the current CPU number > + * > + * Iterate over online CPUs & configure the other/redirect register region to > + * access each CPUs GIC local register block, which can be accessed from the > + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or > + * their derivatives. > + * > + * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER > + * cannot be clobbered. > + */ > +#define gic_with_each_online_cpu(cpu) \ nit: please keep the kernel convention of using 'for_each'. This makes it far easier to grep for such iterators when doing bulk refactoring. Also, since there is a requirement to hold the gic_lock, please add a lockdep_assert_held() in the loop so that it can be checked with a lockdep kernel. > + for ((cpu) = __gic_with_next_online_cpu(-1); \ > + (cpu) = __gic_with_next_online_cpu(cpu), \ > + (cpu) < nr_cpu_ids;) > + > static void gic_clear_pcpu_masks(unsigned int intr) > { > unsigned int i; > @@ -357,10 +396,8 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) > cd->mask = false; > > spin_lock_irqsave(&gic_lock, flags); > - for_each_online_cpu(cpu) { > - write_gic_vl_other(mips_cm_vp_id(cpu)); > + gic_with_each_online_cpu(cpu) > write_gic_vo_rmask(BIT(intr)); > - } > spin_unlock_irqrestore(&gic_lock, flags); > } > > @@ -375,10 +412,8 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) > cd->mask = true; > > spin_lock_irqsave(&gic_lock, flags); > - for_each_online_cpu(cpu) { > - write_gic_vl_other(mips_cm_vp_id(cpu)); > + gic_with_each_online_cpu(cpu) > write_gic_vo_smask(BIT(intr)); > - } > spin_unlock_irqrestore(&gic_lock, flags); > } > > @@ -532,10 +567,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, > return -EPERM; > > spin_lock_irqsave(&gic_lock, flags); > - for_each_online_cpu(cpu) { > - write_gic_vl_other(mips_cm_vp_id(cpu)); > + gic_with_each_online_cpu(cpu) > write_gic_vo_map(mips_gic_vx_map_reg(intr), map); > - } > spin_unlock_irqrestore(&gic_lock, flags); > > return 0; Thanks, M. -- Without deviation from the norm, progress is not possible.