[GIT PULL] MIPS fixes for v6.18

[GIT PULL] MIPS fixes for v6.18

[Thomas Bogendoerfer]

The following changes since commit e9a6fb0bcdd7609be6969112f3fbfcce3b1d4a7c:

  Linux 6.18-rc5 (2025-11-09 15:10:19 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_1

for you to fetch changes up to 14b46ba92bf547508b4a49370c99aba76cb53b53:

  MIPS: kernel: Fix random segmentation faults (2025-11-21 13:24:05 +0100)

----------------------------------------------------------------
- Fix CPU type in DT for econet
- Fix for Malta PCI MMIO breakage for SOC-it
- Fix TLB shutdown caused by iniital uniquification
- Fix random seg faults

----------------------------------------------------------------
Aleksander Jan Bajkowski (1):
      mips: dts: econet: fix EN751221 core type

Maciej W. Rozycki (2):
      MIPS: Malta: Fix !EVA SOC-it PCI MMIO
      MIPS: mm: Prevent a TLB shutdown on initial uniquification

Thomas Bogendoerfer (1):
      MIPS: kernel: Fix random segmentation faults

 arch/mips/boot/dts/econet/en751221.dtsi |   2 +-
 arch/mips/kernel/process.c              |   2 +-
 arch/mips/mm/tlb-r4k.c                  | 100 ++++++++++++++++++++------------
 arch/mips/mti-malta/malta-init.c        |  20 ++++---
 4 files changed, 78 insertions(+), 46 deletions(-)

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [GIT PULL] MIPS fixes for v6.18

[pr-tracker-bot]

The pull request you sent on Sat, 22 Nov 2025 21:47:53 +0100:

> git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_1

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d13f3ac64efb868d09cb2726b1e84929afe90235

Thank you!

-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html

Re: [GIT PULL] MIPS fixes for v6.18

[Gregory CLEMENT]

Hello Thomas,

> The following changes since commit e9a6fb0bcdd7609be6969112f3fbfcce3b1d4a7c:
>
>   Linux 6.18-rc5 (2025-11-09 15:10:19 -0800)
>
> are available in the Git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_1
>
> for you to fetch changes up to 14b46ba92bf547508b4a49370c99aba76cb53b53:
>
>   MIPS: kernel: Fix random segmentation faults (2025-11-21 13:24:05 +0100)
>
> ----------------------------------------------------------------
> - Fix CPU type in DT for econet
> - Fix for Malta PCI MMIO breakage for SOC-it
> - Fix TLB shutdown caused by iniital uniquification
> - Fix random seg faults
>
> ----------------------------------------------------------------
> Aleksander Jan Bajkowski (1):
>       mips: dts: econet: fix EN751221 core type
>
> Maciej W. Rozycki (2):
>       MIPS: Malta: Fix !EVA SOC-it PCI MMIO
>       MIPS: mm: Prevent a TLB shutdown on initial uniquification

Today, the kernel v6.18-rc7 no longer boots on EyeQ5 and EyeQ6H (MIPS
I6500)-based boards. After a git bisect between v6.18-rc6 and v6.18-rc7,
we found that the culprit is the commit "MIPS: mm: Prevent a TLB
shutdown on initial uniquification".

Here is the log from a vanilla v6.18-rc7:

Linux version 6.18.0-rc7 (gclement@BLaptop) (mips-img-linux-gnu-gcc (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 11.2.0, GNU ld (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 2.31.1) #1015 SMP Mon Nov 24 14:48:06 CET 2025
CPU0 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
MIPS: machine is Mobile EyeQ6H MP6 Evaluation board
earlycon: pl11 at MMIO32 0x00000000d3331000 (options '921600n8')
printk: legacy bootconsole [pl11] enabled
Initrd not found or empty - disabling initrd
OF: reserved mem: Reserved memory: No reserved-memory node in the DT
VP topology {4,4,4,4},{4,4,4,4} total 32
VP Local Reset Exception Base support 47 bits address
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
Zone ranges:
  Normal   [mem 0x0000000100000000-0x00000001ffffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000100000000-0x00000001ffffffff]
Initmem setup node 0 [mem 0x0000000100000000-0x00000001ffffffff]
percpu: Embedded 6 pages/cpu s46496 r8192 d43616 u98304
Kernel command line: earlycon
printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
Dentry cache hash table entries: 524288 (order: 8, 4194304 bytes, linear)
Inode-cache hash table entries: 262144 (order: 7, 2097152 bytes, linear)

and with the commit reverted:

Linux version 6.18.0-rc7-00001-g67a4ac15d5c5 (gclement@BLaptop) (mips-img-linux-gnu-gcc (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 11.2.0, GNU ld (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 2.31.1) #1016 SMP Mon Nov 24 16:17:40 CET 2025
CPU0 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
MIPS: machine is Mobile EyeQ6H MP6 Evaluation board
earlycon: pl11 at MMIO32 0x00000000d3331000 (options '921600n8')
printk: legacy bootconsole [pl11] enabled
Initrd not found or empty - disabling initrd
OF: reserved mem: Reserved memory: No reserved-memory node in the DT
VP topology {4,4,4,4},{4,4,4,4} total 32
VP Local Reset Exception Base support 47 bits address
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
Zone ranges:
  Normal   [mem 0x0000000100000000-0x00000001ffffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000100000000-0x00000001ffffffff]
Initmem setup node 0 [mem 0x0000000100000000-0x00000001ffffffff]
percpu: Embedded 6 pages/cpu s46496 r8192 d43616 u98304
Kernel command line: earlycon
printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
Dentry cache hash table entries: 524288 (order: 8, 4194304 bytes, linear)
Inode-cache hash table entries: 262144 (order: 7, 2097152 bytes, linear)
ebase(0x0000000100610000) should better be in KSeg0
Cache parity protection enabled
MAAR configuration:
  [0]: 0x0000000100000000-0x00000001ffffffff speculate
  [1]: disabled
  [2]: disabled
Built 1 zonelists, mobility grouping on.  Total pages: 262144
mem auto-init: stack:off, heap alloc:off, heap free:off
SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=16, Nodes=1
rcu: Hierarchical RCU implementation.
        Tracing variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
RCU Tasks Trace: Setting shift to 4 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=16.
NR_IRQS: 256
rcu: srcu_init: Setting srcu_struct sizes based on contention.
clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0x19e832f0bf5, max_idle_ns: 440795257573 ns
sched_clock: 64 bits at 1797MHz, resolution 0ns, wraps every 4398046511103ns
clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 2126812937 ns
Console: colour dummy device 80x25
printk: legacy console [tty0] enabled
printk: legacy bootconsole [pl11] disabled
Linux version 6.18.0-rc7-00001-g67a4ac15d5c5 (gclement@BLaptop) (mips-img-linux-gnu-gcc (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 11.2.0, GNU ld (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 2.31.1) #1016 SMP Mon Nov 24 16:17:40 CET 2025
CPU0 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
MIPS: machine is Mobile EyeQ6H MP6 Evaluation board
earlycon: pl11 at MMIO32 0x00000000d3331000 (options '921600n8')
printk: legacy bootconsole [pl11] enabled
Initrd not found or empty - disabling initrd
OF: reserved mem: Reserved memory: No reserved-memory node in the DT
VP topology {4,4,4,4},{4,4,4,4} total 32
VP Local Reset Exception Base support 47 bits address
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
Zone ranges:
  Normal   [mem 0x0000000100000000-0x00000001ffffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000100000000-0x00000001ffffffff]
Initmem setup node 0 [mem 0x0000000100000000-0x00000001ffffffff]
percpu: Embedded 6 pages/cpu s46496 r8192 d43616 u98304
Kernel command line: earlycon
printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
Dentry cache hash table entries: 524288 (order: 8, 4194304 bytes, linear)
Inode-cache hash table entries: 262144 (order: 7, 2097152 bytes, linear)
ebase(0x0000000100610000) should better be in KSeg0
Cache parity protection enabled
MAAR configuration:
  [0]: 0x0000000100000000-0x00000001ffffffff speculate
  [1]: disabled
  [2]: disabled
Built 1 zonelists, mobility grouping on.  Total pages: 262144
mem auto-init: stack:off, heap alloc:off, heap free:off
SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=16, Nodes=1
rcu: Hierarchical RCU implementation.
        Tracing variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
RCU Tasks Trace: Setting shift to 4 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=16.
NR_IRQS: 256
rcu: srcu_init: Setting srcu_struct sizes based on contention.
clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0x19e832f0bf5, max_idle_ns: 440795257573 ns
sched_clock: 64 bits at 1797MHz, resolution 0ns, wraps every 4398046511103ns
clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 2126812937 ns
Console: colour dummy device 80x25
printk: legacy console [tty0] enabled
printk: legacy bootconsole [pl11] disabled
Calibrating delay loop... 1795.07 BogoMIPS (lpj=3590144)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 8192 (order: 2, 65536 bytes, linear)
Mountpoint-cache hash table entries: 8192 (order: 2, 65536 bytes, linear)
HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken
MMID support disabled due to hardware support issue
rcu: Hierarchical SRCU implementation.
rcu:    Max phase no-delay instances is 1000.
Timer migration: 2 hierarchy levels; 8 children per group; 2 crossnode level
smp: Bringing up secondary CPUs ...
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU4 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU8 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU12 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Counter synchronization [CPU#0 -> CPU#4]: passed
Counter synchronization [CPU#0 -> CPU#8]: passed
Counter synchronization [CPU#0 -> CPU#12]: passed
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU1 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU2 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU3 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU5 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU6 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU7 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU9 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU10 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU11 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU13 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU14 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
CPU15 revision is: 0001b031 (MIPS I6500)
FPU revision is: 20f30320
MSA revision is: 00000320
Counter synchronization [CPU#0 -> CPU#1]:
Measured 3 cycles counter warp between CPUs
Counter synchronization [CPU#0 -> CPU#2]:
Measured 19 cycles counter warp between CPUs
Counter synchronization [CPU#0 -> CPU#3]:
Measured 8 cycles counter warp between CPUs
Counter synchronization [CPU#0 -> CPU#5]: passed
Counter synchronization [CPU#0 -> CPU#6]: passed
Counter synchronization [CPU#0 -> CPU#7]: passed
Counter synchronization [CPU#0 -> CPU#9]: passed
Counter synchronization [CPU#0 -> CPU#10]: passed
Counter synchronization [CPU#0 -> CPU#11]:
Measured 6 cycles counter warp between CPUs
Counter synchronization [CPU#0 -> CPU#13]: passed
Counter synchronization [CPU#0 -> CPU#14]: passed
Counter synchronization [CPU#0 -> CPU#15]: passed
smp: Brought up 1 node, 16 CPUs
Memory: 4143504K/4194304K available (11084K kernel code, 918K rwdata, 1976K rodata, 5776K init, 344K bss, 44288K reserved, 0K cma-reserved)
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
posixtimers hash table entries: 8192 (order: 3, 131072 bytes, linear)
futex hash table entries: 4096 (524288 bytes on 1 NUMA nodes, total 512 KiB, linear).
pinctrl core: initialized pinctrl subsystem
NET: Registered PF_NETLINK/PF_ROUTE protocol family
Serial: AMBA PL011 UART driver
d3331000.serial: ttyAMA0 at MMIO 0xd3331000 (irq = 42, base_baud = 0) is a PL011 rev3
printk: console [ttyAMA0] enabled
SCSI subsystem initialized
vgaarb: loaded
clocksource: Switched to clocksource GIC
NET: Registered PF_INET protocol family
IP idents hash table entries: 65536 (order: 5, 524288 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 2048 (order: 1, 32768 bytes, linear)
Table-perturb hash table entries: 65536 (order: 4, 262144 bytes, linear)
TCP established hash table entries: 32768 (order: 4, 262144 bytes, linear)
TCP bind hash table entries: 32768 (order: 6, 1048576 bytes, linear)
TCP: Hash tables configured (established 32768 bind 32768)
UDP hash table entries: 2048 (order: 3, 131072 bytes, linear)
UDP-Lite hash table entries: 2048 (order: 3, 131072 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp-with-tls transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
workingset: timestamp_bits=46 max_order=18 bucket_order=0
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
nfs4filelayout_init: NFSv4 File Layout Driver Registering...
nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
fuse: init (API version 7.45)
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
io scheduler mq-deadline registered
io scheduler kyber registered
io scheduler bfq registered
pinctrl-single d3337000.pinctrl: 44 pins, size 176
pinctrl-single d3357000.pinctrl: 44 pins, size 176
pinctrl-single d8014000.pinctrl: 62 pins, size 248
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
CAN device driver interface
i2c_dev: i2c /dev entries driver
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
NET: Registered PF_INET6 protocol family
Segment Routing with IPv6
In-situ OAM (IOAM) with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered PF_PACKET protocol family
NET: Registered PF_KEY protocol family
can: controller area network core
NET: Registered PF_CAN protocol family
can: raw protocol
can: broadcast manager protocol
can: netlink gateway - max_hops=1
Key type dns_resolver registered
registered taskstats version 1
Key type .fscrypt registered
Key type fscrypt-provisioning registered
clk: Disabling unused clocks
mmc0: SDHCI controller on d8010000.mmc [d8010000.mmc] using ADMA 64-bit
Freeing unused kernel image (initmem) memory: 5776K
This architecture does not have kernel memory protection.
Run /init as init process
mmc0: new HS400 Enhanced strobe MMC card at address 0001
mmcblk0: mmc0:0001 G1M15N 119 GiB
GPT:Primary header thinks Alt. header is not at the end of the disk.
GPT:31 != 248643583
GPT:Alternate GPT header not at the end of the disk.
GPT:31 != 248643583
GPT: Use GNU Parted to correct GPT errors.
 mmcblk0: p1 p2 p3
mmcblk0boot0: mmc0:0001 G1M15N 31.5 MiB
mmcblk0boot1: mmc0:0001 G1M15N 31.5 MiB
mmcblk0rpmb: mmc0:0001 G1M15N 4.00 MiB, chardev (252:0)
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Saving 256 bits of non-creditable seed for next boot
Starting network: OK

Welcome to Buildroot
buildroot login: 

We are working on a fix for this issue. If no solution is identified by
version 6.18, the changes may need to be reverted.

Gregory


>
> Thomas Bogendoerfer (1):
>       MIPS: kernel: Fix random segmentation faults
>
>  arch/mips/boot/dts/econet/en751221.dtsi |   2 +-
>  arch/mips/kernel/process.c              |   2 +-
>  arch/mips/mm/tlb-r4k.c                  | 100 ++++++++++++++++++++------------
>  arch/mips/mti-malta/malta-init.c        |  20 ++++---
>  4 files changed, 78 insertions(+), 46 deletions(-)
>
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]
>

-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [GIT PULL] MIPS fixes for v6.18

[Thomas Bogendoerfer]

On Mon, Nov 24, 2025 at 04:46:44PM +0100, Gregory CLEMENT wrote:
> Hello Thomas,
> 
> > The following changes since commit e9a6fb0bcdd7609be6969112f3fbfcce3b1d4a7c:
> >
> >   Linux 6.18-rc5 (2025-11-09 15:10:19 -0800)
> >
> > are available in the Git repository at:
> >
> >   git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_1
> >
> > for you to fetch changes up to 14b46ba92bf547508b4a49370c99aba76cb53b53:
> >
> >   MIPS: kernel: Fix random segmentation faults (2025-11-21 13:24:05 +0100)
> >
> > ----------------------------------------------------------------
> > - Fix CPU type in DT for econet
> > - Fix for Malta PCI MMIO breakage for SOC-it
> > - Fix TLB shutdown caused by iniital uniquification
> > - Fix random seg faults
> >
> > ----------------------------------------------------------------
> > Aleksander Jan Bajkowski (1):
> >       mips: dts: econet: fix EN751221 core type
> >
> > Maciej W. Rozycki (2):
> >       MIPS: Malta: Fix !EVA SOC-it PCI MMIO
> >       MIPS: mm: Prevent a TLB shutdown on initial uniquification
> 
> Today, the kernel v6.18-rc7 no longer boots on EyeQ5 and EyeQ6H (MIPS
> I6500)-based boards. After a git bisect between v6.18-rc6 and v6.18-rc7,
> we found that the culprit is the commit "MIPS: mm: Prevent a TLB
> shutdown on initial uniquification".
> 
> Here is the log from a vanilla v6.18-rc7:
> 
> Linux version 6.18.0-rc7 (gclement@BLaptop) (mips-img-linux-gnu-gcc (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 11.2.0, GNU ld (Codescape GNU Tools 2021.09-01 for MIPS IMG Linux) 2.31.1) #1015 SMP Mon Nov 24 14:48:06 CET 2025
> CPU0 revision is: 0001b031 (MIPS I6500)
> FPU revision is: 20f30320
> MSA revision is: 00000320
> MIPS: machine is Mobile EyeQ6H MP6 Evaluation board
> earlycon: pl11 at MMIO32 0x00000000d3331000 (options '921600n8')
> printk: legacy bootconsole [pl11] enabled
> Initrd not found or empty - disabling initrd
> OF: reserved mem: Reserved memory: No reserved-memory node in the DT
> VP topology {4,4,4,4},{4,4,4,4} total 32
> VP Local Reset Exception Base support 47 bits address
> Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
> Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 64 bytes
> MIPS secondary cache 1024kB, 16-way, linesize 64 bytes.
> Zone ranges:
>   Normal   [mem 0x0000000100000000-0x00000001ffffffff]
> Movable zone start for each node
> Early memory node ranges
>   node   0: [mem 0x0000000100000000-0x00000001ffffffff]
> Initmem setup node 0 [mem 0x0000000100000000-0x00000001ffffffff]
> percpu: Embedded 6 pages/cpu s46496 r8192 d43616 u98304
> Kernel command line: earlycon
> printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
> Dentry cache hash table entries: 524288 (order: 8, 4194304 bytes, linear)
> Inode-cache hash table entries: 262144 (order: 7, 2097152 bytes, linear)
> 
> and with the commit reverted:

I see something similair on a Octeon board with the addition

Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in: r4k_tlb_uniquify+0x31c/0x320

Maciej, any idea ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [GIT PULL] MIPS fixes for v6.18

[Thomas Bogendoerfer]

On Mon, Nov 24, 2025 at 04:46:44PM +0100, Gregory CLEMENT wrote:
> Hello Thomas,
> 
> > The following changes since commit e9a6fb0bcdd7609be6969112f3fbfcce3b1d4a7c:
> >
> >   Linux 6.18-rc5 (2025-11-09 15:10:19 -0800)
> >
> > are available in the Git repository at:
> >
> >   git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_1
> >
> > for you to fetch changes up to 14b46ba92bf547508b4a49370c99aba76cb53b53:
> >
> >   MIPS: kernel: Fix random segmentation faults (2025-11-21 13:24:05 +0100)
> >
> > ----------------------------------------------------------------
> > - Fix CPU type in DT for econet
> > - Fix for Malta PCI MMIO breakage for SOC-it
> > - Fix TLB shutdown caused by iniital uniquification
> > - Fix random seg faults
> >
> > ----------------------------------------------------------------
> > Aleksander Jan Bajkowski (1):
> >       mips: dts: econet: fix EN751221 core type
> >
> > Maciej W. Rozycki (2):
> >       MIPS: Malta: Fix !EVA SOC-it PCI MMIO
> >       MIPS: mm: Prevent a TLB shutdown on initial uniquification
> 
> Today, the kernel v6.18-rc7 no longer boots on EyeQ5 and EyeQ6H (MIPS
> I6500)-based boards. After a git bisect between v6.18-rc6 and v6.18-rc7,
> we found that the culprit is the commit "MIPS: mm: Prevent a TLB
> shutdown on initial uniquification".
> 
> Here is the log from a vanilla v6.18-rc7:

[..]

I guess your cores have more than 64 TLB entries. The Octeon CPU has
256 entries... Patch below fixes the issue there.

Thomas.

From b74abcb21103519ae48726c715d39a6aa3f57462 Mon Sep 17 00:00:00 2001
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date: Mon, 24 Nov 2025 22:46:43 +0100
Subject: [PATCH] MIPS: mm: kmalloc tlb_vpn array to avoid stack overflow

Latest MIPS cores could have much more than 64 TLB entries, therefore
allocate array for unification instead of placing a too small array
on stack.

Fixes: 9f048fa48740 ("MIPS: mm: Prevent a TLB shutdown on initial uniquification")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/mm/tlb-r4k.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 3facf7cc6c7d..577055b50c41 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -524,15 +524,19 @@ static int r4k_vpn_cmp(const void *a, const void *b)
  */
 static void r4k_tlb_uniquify(void)
 {
-	unsigned long tlb_vpns[1 << MIPS_CONF1_TLBS_SIZE];
 	int tlbsize = current_cpu_data.tlbsize;
 	int start = num_wired_entries();
+	unsigned long *tlb_vpns;
 	unsigned long vpn_mask;
 	int cnt, ent, idx, i;
 
 	vpn_mask = GENMASK(cpu_vmbits - 1, 13);
 	vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
 
+	tlb_vpns = kmalloc_array(tlbsize, sizeof(unsigned long), GFP_KERNEL);
+	if (!tlb_vpns)
+		return; /* pray local_flush_tlb_all() is good enough */
+
 	htw_stop();
 
 	for (i = start, cnt = 0; i < tlbsize; i++, cnt++) {
@@ -585,6 +589,7 @@ static void r4k_tlb_uniquify(void)
 	tlbw_use_hazard();
 	htw_start();
 	flush_micro_tlb();
+	kfree(tlb_vpns);
 }
 
 /*
-- 
2.43.0

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [GIT PULL] MIPS fixes for v6.18

[Maciej W. Rozycki]

On Mon, 24 Nov 2025, Thomas Bogendoerfer wrote:

> > > Maciej W. Rozycki (2):
> > >       MIPS: Malta: Fix !EVA SOC-it PCI MMIO
> > >       MIPS: mm: Prevent a TLB shutdown on initial uniquification
> > 
> > Today, the kernel v6.18-rc7 no longer boots on EyeQ5 and EyeQ6H (MIPS
> > I6500)-based boards. After a git bisect between v6.18-rc6 and v6.18-rc7,
> > we found that the culprit is the commit "MIPS: mm: Prevent a TLB
> > shutdown on initial uniquification".
> > 
> > Here is the log from a vanilla v6.18-rc7:
> 
> [..]
> 
> I guess your cores have more than 64 TLB entries. The Octeon CPU has
> 256 entries... Patch below fixes the issue there.
> 
> Thomas.
> 
> >From b74abcb21103519ae48726c715d39a6aa3f57462 Mon Sep 17 00:00:00 2001
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Date: Mon, 24 Nov 2025 22:46:43 +0100
> Subject: [PATCH] MIPS: mm: kmalloc tlb_vpn array to avoid stack overflow
> 
> Latest MIPS cores could have much more than 64 TLB entries, therefore
> allocate array for unification instead of placing a too small array
> on stack.

 Thank you for chasing this up.

 Indeed, in the absence of a cross-reference from Config1.MMUSize in the 
ISA manual I missed the somewhat recent addition of Config4.MMUSizeExt and 
VTLB/FTLB MMU features I haven't dealt with before.  I've looked through 
the relevant documents and ISTM there's nothing else needed here so let's 
hope your fix covers it all.

 For the record, the I6500 has a documented TLB size of 16 VTLB + 512 FTLB 
entries and the array needs to hold them all.  Though for VTLB/FTLB we 
necessarily rely on the EntryHi.EHINV feature, which means we could skip 
the call to `r4k_tlb_uniquify' altogether.  Something for a possible later 
improvement, I suppose.

> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
> index 3facf7cc6c7d..577055b50c41 100644
> --- a/arch/mips/mm/tlb-r4k.c
> +++ b/arch/mips/mm/tlb-r4k.c
> @@ -524,15 +524,19 @@ static int r4k_vpn_cmp(const void *a, const void *b)
>   */
>  static void r4k_tlb_uniquify(void)
>  {
> -	unsigned long tlb_vpns[1 << MIPS_CONF1_TLBS_SIZE];
>  	int tlbsize = current_cpu_data.tlbsize;
>  	int start = num_wired_entries();
> +	unsigned long *tlb_vpns;
>  	unsigned long vpn_mask;
>  	int cnt, ent, idx, i;
>  
>  	vpn_mask = GENMASK(cpu_vmbits - 1, 13);
>  	vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
>  
> +	tlb_vpns = kmalloc_array(tlbsize, sizeof(unsigned long), GFP_KERNEL);
> +	if (!tlb_vpns)
> +		return; /* pray local_flush_tlb_all() is good enough */

 I can't say I'm particularly happy with this bail-out hack, but then I 
have nothing better in my mind right now, so OK, but can you please make 
the comment a proper sentence (starting with a capital letter and ending 
with a full stop)?

  Maciej

Re: [GIT PULL] MIPS fixes for v6.18

[Thomas Bogendoerfer]

On Tue, Nov 25, 2025 at 07:32:16AM +0000, Maciej W. Rozycki wrote:
> On Mon, 24 Nov 2025, Thomas Bogendoerfer wrote:
> 
> > > > Maciej W. Rozycki (2):
> > > >       MIPS: Malta: Fix !EVA SOC-it PCI MMIO
> > > >       MIPS: mm: Prevent a TLB shutdown on initial uniquification
> > > 
> > > Today, the kernel v6.18-rc7 no longer boots on EyeQ5 and EyeQ6H (MIPS
> > > I6500)-based boards. After a git bisect between v6.18-rc6 and v6.18-rc7,
> > > we found that the culprit is the commit "MIPS: mm: Prevent a TLB
> > > shutdown on initial uniquification".
> > > 
> > > Here is the log from a vanilla v6.18-rc7:
> > 
> > [..]
> > 
> > I guess your cores have more than 64 TLB entries. The Octeon CPU has
> > 256 entries... Patch below fixes the issue there.
> > 
> > Thomas.
> > 
> > >From b74abcb21103519ae48726c715d39a6aa3f57462 Mon Sep 17 00:00:00 2001
> > From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Date: Mon, 24 Nov 2025 22:46:43 +0100
> > Subject: [PATCH] MIPS: mm: kmalloc tlb_vpn array to avoid stack overflow
> > 
> > Latest MIPS cores could have much more than 64 TLB entries, therefore
> > allocate array for unification instead of placing a too small array
> > on stack.
> 
>  Thank you for chasing this up.
> 
>  Indeed, in the absence of a cross-reference from Config1.MMUSize in the 
> ISA manual I missed the somewhat recent addition of Config4.MMUSizeExt and 
> VTLB/FTLB MMU features I haven't dealt with before.  I've looked through 
> the relevant documents and ISTM there's nothing else needed here so let's 
> hope your fix covers it all.
> 
>  For the record, the I6500 has a documented TLB size of 16 VTLB + 512 FTLB 
> entries and the array needs to hold them all.  Though for VTLB/FTLB we 
> necessarily rely on the EntryHi.EHINV feature, which means we could skip 
> the call to `r4k_tlb_uniquify' altogether.  Something for a possible later 
> improvement, I suppose.
> 
> > diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
> > index 3facf7cc6c7d..577055b50c41 100644
> > --- a/arch/mips/mm/tlb-r4k.c
> > +++ b/arch/mips/mm/tlb-r4k.c
> > @@ -524,15 +524,19 @@ static int r4k_vpn_cmp(const void *a, const void *b)
> >   */
> >  static void r4k_tlb_uniquify(void)
> >  {
> > -	unsigned long tlb_vpns[1 << MIPS_CONF1_TLBS_SIZE];
> >  	int tlbsize = current_cpu_data.tlbsize;
> >  	int start = num_wired_entries();
> > +	unsigned long *tlb_vpns;
> >  	unsigned long vpn_mask;
> >  	int cnt, ent, idx, i;
> >  
> >  	vpn_mask = GENMASK(cpu_vmbits - 1, 13);
> >  	vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
> >  
> > +	tlb_vpns = kmalloc_array(tlbsize, sizeof(unsigned long), GFP_KERNEL);
> > +	if (!tlb_vpns)
> > +		return; /* pray local_flush_tlb_all() is good enough */
> 
>  I can't say I'm particularly happy with this bail-out hack, but then I 
> have nothing better in my mind right now, so OK, but can you please make 
> the comment a proper sentence (starting with a capital letter and ending 
> with a full stop)?

I'll add a WARN_ON() to inform users about the issue, but as this is
pretty early during boot, I don't think anybody will see it.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [GIT PULL] MIPS fixes for v6.18

[Maciej W. Rozycki]

On Tue, 25 Nov 2025, Thomas Bogendoerfer wrote:

> > > diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
> > > index 3facf7cc6c7d..577055b50c41 100644
> > > --- a/arch/mips/mm/tlb-r4k.c
> > > +++ b/arch/mips/mm/tlb-r4k.c
> > > @@ -524,15 +524,19 @@ static int r4k_vpn_cmp(const void *a, const void *b)
> > >   */
> > >  static void r4k_tlb_uniquify(void)
> > >  {
> > > -	unsigned long tlb_vpns[1 << MIPS_CONF1_TLBS_SIZE];
> > >  	int tlbsize = current_cpu_data.tlbsize;
> > >  	int start = num_wired_entries();
> > > +	unsigned long *tlb_vpns;
> > >  	unsigned long vpn_mask;
> > >  	int cnt, ent, idx, i;
> > >  
> > >  	vpn_mask = GENMASK(cpu_vmbits - 1, 13);
> > >  	vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
> > >  
> > > +	tlb_vpns = kmalloc_array(tlbsize, sizeof(unsigned long), GFP_KERNEL);
> > > +	if (!tlb_vpns)
> > > +		return; /* pray local_flush_tlb_all() is good enough */
> > 
> >  I can't say I'm particularly happy with this bail-out hack, but then I 
> > have nothing better in my mind right now, so OK, but can you please make 
> > the comment a proper sentence (starting with a capital letter and ending 
> > with a full stop)?
> 
> I'll add a WARN_ON() to inform users about the issue, but as this is
> pretty early during boot, I don't think anybody will see it.

 Umm, `kmalloc' by default warns about allocation failures anyway and if 
it does cause a hang or crash as seen with these reports, it should be 
hard to miss.

 Then it seems unlikely enough an allocation will fail of say 4KiB for a 
very large TLB to add any special handling for it given that the vast 
majority of systems seems not to need this TLB preinitialisation in most 
cases.  It just feels odd to me.

  Maciej

Re: [GIT PULL] MIPS fixes for v6.18

[Gregory CLEMENT]

Hello Thomas,

> On Mon, Nov 24, 2025 at 04:46:44PM +0100, Gregory CLEMENT wrote:
>> Hello Thomas,
>> 
>> > The following changes since commit e9a6fb0bcdd7609be6969112f3fbfcce3b1d4a7c:
>> >
>> >   Linux 6.18-rc5 (2025-11-09 15:10:19 -0800)
>> >
>> > are available in the Git repository at:
>> >
>> >   git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_1
>> >
>> > for you to fetch changes up to 14b46ba92bf547508b4a49370c99aba76cb53b53:
>> >
>> >   MIPS: kernel: Fix random segmentation faults (2025-11-21 13:24:05 +0100)
>> >
>> > ----------------------------------------------------------------
>> > - Fix CPU type in DT for econet
>> > - Fix for Malta PCI MMIO breakage for SOC-it
>> > - Fix TLB shutdown caused by iniital uniquification
>> > - Fix random seg faults
>> >
>> > ----------------------------------------------------------------
>> > Aleksander Jan Bajkowski (1):
>> >       mips: dts: econet: fix EN751221 core type
>> >
>> > Maciej W. Rozycki (2):
>> >       MIPS: Malta: Fix !EVA SOC-it PCI MMIO
>> >       MIPS: mm: Prevent a TLB shutdown on initial uniquification
>> 
>> Today, the kernel v6.18-rc7 no longer boots on EyeQ5 and EyeQ6H (MIPS
>> I6500)-based boards. After a git bisect between v6.18-rc6 and v6.18-rc7,
>> we found that the culprit is the commit "MIPS: mm: Prevent a TLB
>> shutdown on initial uniquification".
>> 
>> Here is the log from a vanilla v6.18-rc7:
>
> [..]
>
> I guess your cores have more than 64 TLB entries. The Octeon CPU has
> 256 entries... Patch below fixes the issue there.
>

I have applied this patch and tested it on EyeQ5 and EyeQ6H-based
boards, and it booted successfully.

you can add my

Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Thanks,

Gregory

> Thomas.
>
> From b74abcb21103519ae48726c715d39a6aa3f57462 Mon Sep 17 00:00:00 2001
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Date: Mon, 24 Nov 2025 22:46:43 +0100
> Subject: [PATCH] MIPS: mm: kmalloc tlb_vpn array to avoid stack overflow
>
> Latest MIPS cores could have much more than 64 TLB entries, therefore
> allocate array for unification instead of placing a too small array
> on stack.
>
> Fixes: 9f048fa48740 ("MIPS: mm: Prevent a TLB shutdown on initial uniquification")
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> ---
>  arch/mips/mm/tlb-r4k.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
> index 3facf7cc6c7d..577055b50c41 100644
> --- a/arch/mips/mm/tlb-r4k.c
> +++ b/arch/mips/mm/tlb-r4k.c
> @@ -524,15 +524,19 @@ static int r4k_vpn_cmp(const void *a, const void *b)
>   */
>  static void r4k_tlb_uniquify(void)
>  {
> -	unsigned long tlb_vpns[1 << MIPS_CONF1_TLBS_SIZE];
>  	int tlbsize = current_cpu_data.tlbsize;
>  	int start = num_wired_entries();
> +	unsigned long *tlb_vpns;
>  	unsigned long vpn_mask;
>  	int cnt, ent, idx, i;
>  
>  	vpn_mask = GENMASK(cpu_vmbits - 1, 13);
>  	vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
>  
> +	tlb_vpns = kmalloc_array(tlbsize, sizeof(unsigned long), GFP_KERNEL);
> +	if (!tlb_vpns)
> +		return; /* pray local_flush_tlb_all() is good enough */
> +
>  	htw_stop();
>  
>  	for (i = start, cnt = 0; i < tlbsize; i++, cnt++) {
> @@ -585,6 +589,7 @@ static void r4k_tlb_uniquify(void)
>  	tlbw_use_hazard();
>  	htw_start();
>  	flush_micro_tlb();
> +	kfree(tlb_vpns);
>  }
>  
>  /*
> -- 
> 2.43.0
>
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[GIT PULL] MIPS fixes for v6.18

[Thomas Bogendoerfer]

The following changes since commit ac3fd01e4c1efce8f2c054cdeb2ddd2fc0fb150d:

  Linux 6.18-rc7 (2025-11-23 14:53:16 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_2

for you to fetch changes up to 841ecc979b18d3227fad5e2d6a1e6f92688776b5:

  MIPS: mm: kmalloc tlb_vpn array to avoid stack overflow (2025-11-29 13:36:05 +0100)

----------------------------------------------------------------
Fix TLB unification for cores with more than 64 TLB entries

----------------------------------------------------------------
Thomas Bogendoerfer (1):
      MIPS: mm: kmalloc tlb_vpn array to avoid stack overflow

 arch/mips/mm/tlb-r4k.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [GIT PULL] MIPS fixes for v6.18

[pr-tracker-bot]

The pull request you sent on Sat, 29 Nov 2025 21:55:09 +0100:

> git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_6.18_2

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/6bda50f4333fa61c07f04f790fdd4e2c9f4ca610

Thank you!

-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html