From: Marc Zyngier <maz@kernel.org>
To: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Chao-ying Fu <cfu@wavecomp.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Greg Ungerer <gerg@kernel.org>, Hauke Mehrtens <hauke@hauke-m.de>,
Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
Paul Burton <paulburton@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Serge Semin <fancer.lancer@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Tiezhu Yang <yangtiezhu@loongson.cn>,
Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Subject: Re: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support
Date: Mon, 06 Jun 2022 12:47:16 +0100 [thread overview]
Message-ID: <87wndu3tff.wl-maz@kernel.org> (raw)
In-Reply-To: <20220525121030.16054-7-Dragan.Mladjenovic@syrmia.com>
On Wed, 25 May 2022 13:10:24 +0100,
Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com> wrote:
>
> From: Paul Burton <paulburton@kernel.org>
>
> The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of
> multiple clusters to the system. In these systems each cluster contains
> its own GIC, so the GIC isn't truly global any longer. We do have the
> ability to access registers in the GICs of remote clusters using a
> redirect register block much like the redirect register blocks provided
> by the CM & CPC, and configured through the same GCR_REDIRECT register
> that we our mips_cm_lock_other() abstraction builds upon.
>
> It is expected that external interrupts are connected identically to all
> clusters. That is, if we have a device providing an interrupt connected
> to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC
> in the system. This simplifies things somewhat by allowing us for the
> most part to treat the GIC as though it is still truly global, so long
> as we take care to configure interrupts in the cluster that we want them
> affine to.
I can see how this can work for level interrupts, but how does this
work for edge interrupts? Is there any guarantee that the interrupt
will be discarded if routed to a cluster where it isn't configured?
Otherwise, I can imagine plenty of spurious interrupts on affinity
change.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-06-06 11:47 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 12:10 [PATCH v2 00/12] MIPS: Support I6500 multi-cluster configuration Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 01/12] MIPS: CPS: Add a couple of multi-cluster utility functions Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 02/12] MIPS: GIC: Generate redirect block accessors Dragan Mladjenovic
2022-05-25 18:33 ` Jiaxun Yang
2022-05-25 12:10 ` [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() Dragan Mladjenovic
2022-06-06 13:05 ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 04/12] irqchip: mips-gic: Support multi-cluster in gic_with_each_online_cpu() Dragan Mladjenovic
2022-06-06 13:13 ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 05/12] irqchip: mips-gic: Setup defaults in each cluster Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support Dragan Mladjenovic
2022-06-06 11:47 ` Marc Zyngier [this message]
2022-06-07 18:23 ` Jiaxun Yang
2022-06-08 6:05 ` Marc Zyngier
2022-06-09 10:14 ` Jiaxun Yang
2022-06-09 11:54 ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 07/12] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Dragan Mladjenovic
2022-06-27 14:17 ` Dragan Mladjenovic
2022-06-27 14:27 ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 08/12] clocksource: mips-gic-timer: Enable counter when CPUs start Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 09/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 10/12] MIPS: CPS: Introduce struct cluster_boot_config Dragan Mladjenovic
2022-05-25 12:10 ` [PATCH v2 11/12] MIPS: Report cluster in /proc/cpuinfo Dragan Mladjenovic
2022-06-06 13:14 ` Marc Zyngier
2022-06-07 18:27 ` Jiaxun Yang
2022-06-08 6:13 ` Marc Zyngier
2022-05-25 12:10 ` [PATCH v2 12/12] MIPS: CPS: Boot CPUs in secondary clusters Dragan Mladjenovic
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