From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAEA0C43334 for ; Mon, 6 Jun 2022 11:47:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235635AbiFFLrY (ORCPT ); Mon, 6 Jun 2022 07:47:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235633AbiFFLrX (ORCPT ); Mon, 6 Jun 2022 07:47:23 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE7962BEC; Mon, 6 Jun 2022 04:47:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5908BB81813; Mon, 6 Jun 2022 11:47:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06D7FC385A9; Mon, 6 Jun 2022 11:47:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654516039; bh=HMnDmZI2fBwDhe3w4FV+wMwQ+5bxBQ3OaBHYtsOYisA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=qGxtcVZe00HsR+VDZ8FfkIpSGh7EacqrDAf/3Yc2MjSeXhEeq49paBX1amHs45Fqo bFXZPRFS9j4AbazjO3Uo8Yr9CEUkE3iQQmXLa88/wh6eHswTfBx35sHzyMO+rQx7RJ kMHHg/0nAtWjrnjodJMhivF+28vsvEDQjr1Y/ODv7MsTDyDrMu0XqojzK6GjPyT0Kx SKYkTcTleMoa+Ii56W2fKH1Ny8ofpxPaDHuAD0xPeF4zn3VfdXoojSxUdhAnouDaOo O802FRZFUr5eR1mBzdl2anbblH9PtcwgN/EJRh4uDOl2o7Px5KiB51BGCrJunJQQMK nJbHB85cgsvSg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nyBCW-00FtHy-Ll; Mon, 06 Jun 2022 12:47:16 +0100 Date: Mon, 06 Jun 2022 12:47:16 +0100 Message-ID: <87wndu3tff.wl-maz@kernel.org> From: Marc Zyngier To: Dragan Mladjenovic Cc: Thomas Bogendoerfer , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: Re: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support In-Reply-To: <20220525121030.16054-7-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> <20220525121030.16054-7-Dragan.Mladjenovic@syrmia.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Dragan.Mladjenovic@syrmia.com, tsbogend@alpha.franken.de, cfu@wavecomp.com, daniel.lezcano@linaro.org, geert@linux-m68k.org, gerg@kernel.org, hauke@hauke-m.de, ilya.lipnitskiy@gmail.com, jiaxun.yang@flygoat.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, paulburton@kernel.org, peterz@infradead.org, fancer.lancer@gmail.com, tglx@linutronix.de, yangtiezhu@loongson.cn, dragan.mladjenovic@syrmia.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Wed, 25 May 2022 13:10:24 +0100, Dragan Mladjenovic wrote: > > From: Paul Burton > > The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of > multiple clusters to the system. In these systems each cluster contains > its own GIC, so the GIC isn't truly global any longer. We do have the > ability to access registers in the GICs of remote clusters using a > redirect register block much like the redirect register blocks provided > by the CM & CPC, and configured through the same GCR_REDIRECT register > that we our mips_cm_lock_other() abstraction builds upon. > > It is expected that external interrupts are connected identically to all > clusters. That is, if we have a device providing an interrupt connected > to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC > in the system. This simplifies things somewhat by allowing us for the > most part to treat the GIC as though it is still truly global, so long > as we take care to configure interrupts in the cluster that we want them > affine to. I can see how this can work for level interrupts, but how does this work for edge interrupts? Is there any guarantee that the interrupt will be discarded if routed to a cluster where it isn't configured? Otherwise, I can imagine plenty of spurious interrupts on affinity change. Thanks, M. -- Without deviation from the norm, progress is not possible.