From: Marc Zyngier <maz@kernel.org>
To: Huacai Chen <chenhc@lemote.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
linux-mips@vger.kernel.org, Fuxin Zhang <zhangfx@lemote.com>,
Huacai Chen <chenhuacai@gmail.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
stable@vger.kernel.org
Subject: Re: [PATCH 1/3] MIPS: Loongson64: Increase NR_IRQS to 320
Date: Thu, 10 Sep 2020 11:10:02 +0100 [thread overview]
Message-ID: <894f35a7883451c4c2bf91b6181376fb@kernel.org> (raw)
In-Reply-To: <1599624552-17523-1-git-send-email-chenhc@lemote.com>
On 2020-09-09 05:09, Huacai Chen wrote:
> Modernized Loongson64 uses a hierarchical organization for interrupt
> controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
> numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
> is not enough to represent all interrupts, so let's increase NR_IRQS to
> 320.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/mach-loongson64/irq.h
> b/arch/mips/include/asm/mach-loongson64/irq.h
> index f5e362f7..0da3017 100644
> --- a/arch/mips/include/asm/mach-loongson64/irq.h
> +++ b/arch/mips/include/asm/mach-loongson64/irq.h
> @@ -7,7 +7,7 @@
> /* cpu core interrupt numbers */
> #define NR_IRQS_LEGACY 16
> #define NR_MIPS_CPU_IRQS 8
> -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
> +#define NR_IRQS 320
>
> #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Why are you hardcoding a random value instead of bumping the constant
in NR_IRQS?
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-09-10 10:10 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 4:09 [PATCH 1/3] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
2020-09-09 4:09 ` [PATCH 2/3] irqchip/loongson-htvec: Fix initial interrupts clearing Huacai Chen
2020-09-09 4:09 ` [PATCH 3/3] irqchip/loongson-pch-pic: Reserve legacy LPC irqs Huacai Chen
2020-09-10 0:51 ` Jiaxun Yang
2020-09-10 1:40 ` Huacai Chen
2020-09-10 10:08 ` Marc Zyngier
2020-09-11 4:13 ` Huacai Chen
2020-09-11 7:50 ` Marc Zyngier
2020-09-11 10:12 ` Huacai Chen
2020-09-10 16:34 ` Sasha Levin
2020-09-11 0:12 ` Huacai Chen
2020-09-10 10:10 ` Marc Zyngier [this message]
2020-09-11 3:24 ` [PATCH 1/3] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
2020-09-11 7:44 ` Marc Zyngier
2020-09-11 8:43 ` Huacai Chen
2020-09-11 9:03 ` Marc Zyngier
2020-09-11 9:14 ` Huacai Chen
2020-09-11 9:23 ` Marc Zyngier
2020-09-11 9:40 ` Huacai Chen
2020-09-10 16:34 ` Sasha Levin
2020-09-11 0:11 ` Huacai Chen
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