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[78.11.189.27]) by smtp.googlemail.com with ESMTPSA id z22-20020a17090655d600b006d229436793sm5699993ejp.223.2022.03.20.03.54.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Mar 2022 03:54:41 -0700 (PDT) Message-ID: <89f9b797-e4b8-139a-d9e6-ebe71779b943@kernel.org> Date: Sun, 20 Mar 2022 11:54:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format Content-Language: en-US To: Michael Walle , Linus Walleij , Rob Herring , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org References: <20220319204628.1759635-1-michael@walle.cc> <20220319204628.1759635-7-michael@walle.cc> From: Krzysztof Kozlowski In-Reply-To: <20220319204628.1759635-7-michael@walle.cc> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On 19/03/2022 21:46, Michael Walle wrote: > Convert the ocelot-pinctrl device tree binding to the new YAML format. > > Additionally to the original binding documentation, add interrupt > properties which are optional and already used on several SoCs like > SparX-5, Luton, Ocelot and LAN966x but were not documented before. > > Also, on the sparx5 and the lan966x SoCs there are two items for the > reg property. > > Signed-off-by: Michael Walle > --- > .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- > .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++ > 2 files changed, 108 insertions(+), 42 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > deleted file mode 100644 > index 5d84fd299ccf..000000000000 > --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > +++ /dev/null > @@ -1,42 +0,0 @@ > -Microsemi Ocelot pin controller Device Tree Bindings > ----------------------------------------------------- > - > -Required properties: > - - compatible : Should be "mscc,ocelot-pinctrl", > - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", > - "mscc,luton-pinctrl", "mscc,serval-pinctrl", > - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" > - - reg : Address and length of the register set for the device > - - gpio-controller : Indicates this device is a GPIO controller > - - #gpio-cells : Must be 2. > - The first cell is the pin number and the > - second cell specifies GPIO flags, as defined in > - . > - - gpio-ranges : Range of pins managed by the GPIO controller. > - > - > -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin > -configuration documented in pinctrl-bindings.txt. > - > -The following generic properties are supported: > - - function > - - pins > - > -Example: > - gpio: pinctrl@71070034 { > - compatible = "mscc,ocelot-pinctrl"; > - reg = <0x71070034 0x28>; > - gpio-controller; > - #gpio-cells = <2>; > - gpio-ranges = <&gpio 0 0 22>; > - > - uart_pins: uart-pins { > - pins = "GPIO_6", "GPIO_7"; > - function = "uart"; > - }; > - > - uart2_pins: uart2-pins { > - pins = "GPIO_12", "GPIO_13"; > - function = "uart2"; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > new file mode 100644 > index 000000000000..7149a6655623 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microsemi Ocelot pin controller > + > +maintainers: > + - Alexandre Belloni > + - Lars Povlsen > + > +properties: > + compatible: > + enum: > + - microchip,lan966x-pinctrl > + - microchip,sparx5-pinctrl > + - mscc,jaguar2-pinctrl > + - mscc,luton-pinctrl > + - mscc,ocelot-pinctrl > + - mscc,serval-pinctrl > + - mscc,servalt-pinctrl > + > + reg: > + items: > + - description: Base address > + - description: Extended pin configuration registers > + minItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + gpio-ranges: true > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 2 Thanks for the changes in other files, but I think you did not respond to my comments here. Can you address them? Best regards, Krzysztof