From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Serge Semin <fancer.lancer@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width
Date: Mon, 27 May 2024 14:24:01 +0200 [thread overview]
Message-ID: <9d93682c-5da4-43d2-a9fb-f05d3596e066@linaro.org> (raw)
In-Reply-To: <20240511-mips-clks-v1-7-ddb4a10ee9f9@flygoat.com>
On 11/5/24 18:00, Jiaxun Yang wrote:
> Counter width of GIC is configurable and can be read from a
> register.
>
> Use width value from the register for sched_clock.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> drivers/clocksource/mips-gic-timer.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
prev parent reply other threads:[~2024-05-27 12:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-11 16:00 [PATCH 0/7] MIPS: clocksource cumulative enhancements Jiaxun Yang
2024-05-11 16:00 ` [PATCH 1/7] MIPS: csrc-r4k: Refine rating computation Jiaxun Yang
2024-06-01 22:23 ` Maciej W. Rozycki
2024-05-11 16:00 ` [PATCH 2/7] MIPS: csrc-r4k: Apply verification clocksource flags Jiaxun Yang
2024-05-11 16:00 ` [PATCH 3/7] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if 64BIT Jiaxun Yang
2024-06-01 22:30 ` Maciej W. Rozycki
2024-06-04 14:51 ` Jiaxun Yang
2024-05-11 16:00 ` [PATCH 4/7] MIPS: csrc-r4k: Don't register as sched_clock if unfit Jiaxun Yang
2024-05-11 16:00 ` [PATCH 5/7] MIPS: sync-r4k: Rework based on x86 tsc_sync Jiaxun Yang
2024-05-11 16:00 ` [PATCH 6/7] clocksource: mips-gic-timer: Refine rating computation Jiaxun Yang
2024-05-11 16:00 ` [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width Jiaxun Yang
2024-05-27 12:24 ` Philippe Mathieu-Daudé [this message]
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