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Mon, 27 May 2024 05:24:03 -0700 (PDT) Received: from [192.168.69.100] ([176.176.152.134]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-578638009b1sm4178095a12.17.2024.05.27.05.24.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 May 2024 05:24:03 -0700 (PDT) Message-ID: <9d93682c-5da4-43d2-a9fb-f05d3596e066@linaro.org> Date: Mon, 27 May 2024 14:24:01 +0200 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width To: Jiaxun Yang , Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240511-mips-clks-v1-0-ddb4a10ee9f9@flygoat.com> <20240511-mips-clks-v1-7-ddb4a10ee9f9@flygoat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240511-mips-clks-v1-7-ddb4a10ee9f9@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/5/24 18:00, Jiaxun Yang wrote: > Counter width of GIC is configurable and can be read from a > register. > > Use width value from the register for sched_clock. > > Signed-off-by: Jiaxun Yang > --- > drivers/clocksource/mips-gic-timer.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé