messages from 2015-04-21 14:49:01 to 2015-04-25 15:56:41 UTC [more...]
MIPS: BUG() in isolate_lru_pages in mm/vmscan.c?
2015-04-25 15:56 UTC
[PATCH 0/4] spi: spi-ath79: Devicetree support and misc fixes
2015-04-24 17:58 UTC (7+ messages)
` [PATCH 1/4] devicetree: add binding documentation for the AR7100 SPI controller
` [PATCH 2/4] spi: spi-ath79: Add device tree support
` [PATCH 3/4] spi: spi-ath79: Use clk_prepare_enable and clk_disable_unprepare
` [PATCH 4/4] spi: spi-ath79: Set the initial state of CS0
[PATCH] gitignore: Add MIPS vmlinux.32 to the list
2015-04-24 17:27 UTC
[PATCH v4 00/37] JZ4780 & CI20 support
2015-04-24 13:17 UTC (76+ messages)
` [PATCH v4 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix
` [PATCH v4 02/37] devicetree/bindings: add Qi Hardware "
` [PATCH v4 03/37] MIPS: JZ4740: introduce CONFIG_MACH_INGENIC
` [PATCH v4 04/37] MIPS: ingenic: add newer vendor IDs
` [PATCH v4 05/37] MIPS: JZ4740: require & include DT
` [PATCH v4 06/37] MIPS: irq_cpu: declare irqchip table entry
` [PATCH v4 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT
` [PATCH v4 08/37] MIPS: JZ4740: use generic plat_irq_dispatch
` [PATCH v4 09/37] MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c
` [PATCH v4 10/37] devicetree: document Ingenic SoC interrupt controller binding
` [PATCH v4 11/37] MIPS: JZ4740: probe interrupt controller via DT
` [PATCH v4 12/37] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
` [PATCH v4 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller
` [PATCH v4 14/37] MIPS: JZ4740: drop intc debugfs code
` [PATCH v4 15/37] MIPS: JZ4740: remove jz_intc_base global
` [PATCH v4 16/37] MIPS: JZ4740: support >32 interrupts
` [PATCH v4 17/37] MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
` [PATCH v4 18/37] MIPS: JZ4740: read intc base address from DT
` [PATCH v4 19/37] MIPS: JZ4740: avoid JZ4740-specific naming
` [PATCH v4 20/37] MIPS: JZ4740: support newer SoC interrupt controllers
` [PATCH v4 21/37] irqchip: move Ingenic SoC intc driver to drivers/irqchip
` [PATCH v4 22/37] MIPS: JZ4740: call jz4740_clock_init earlier
` [PATCH v4 23/37] MIPS: JZ4740: replace use of jz4740_clock_bdata
` [PATCH v4 24/37] devicetree: add Ingenic CGU binding documentation
` [PATCH v4 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks
` [PATCH v4 26/37] MIPS,clk: migrate JZ4740 to common clock framework
` [PATCH v4 27/37] MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
` [PATCH v4 28/37] MIPS,clk: move jz4740 UDC auto suspend functions "
` [PATCH v4 29/37] MIPS,clk: move jz4740 clock suspend,resume "
` [PATCH v4 30/37] clk: ingenic: add JZ4780 CGU support
` [PATCH v4 31/37] MIPS: JZ4740: remove clock.h
` [PATCH v4 32/37] MIPS: JZ4740: only detect RAM size if not specified in DT
` [PATCH v4 33/37] devicetree: document Ingenic SoC UART binding
` [PATCH v4 34/37] serial: 8250_ingenic: support for Ingenic SoC UARTs
` [PATCH v4 35/37] MIPS: JZ4740: use Ingenic SoC UART driver
` [PATCH v4 36/37] MIPS: ingenic: initial JZ4780 support
` [PATCH v4 37/37] MIPS: ingenic: initial MIPS Creator CI20 support
[PATCH v3 00/12] MIPS: ath79: Add OF support and DTS for TL-WR1043ND
2015-04-24 12:26 UTC (13+ messages)
` [PATCH v3 01/12] devicetree: Add bindings for the SoC of the ATH79 family
` [PATCH v3 02/12] MIPS: ath79: Add basic device tree support
` [PATCH v3 03/12] devicetree: Add bindings for the ATH79 DDR controllers
` [PATCH v3 04/12] devicetree: Add bindings for the ATH79 interrupt controllers
` [PATCH v3 05/12] devicetree: Add bindings for the ATH79 MISC "
` [PATCH v3 06/12] MIPS: ath79: Add OF support to the IRQ controllers
` [PATCH v3 07/12] devicetree: Add bindings for the ATH79 PLL controllers
` [PATCH v3 08/12] MIPS: ath79: Add OF support to the clocks
` [PATCH v3 09/12] devicetree: Add bindings for the ATH79 GPIO controllers
` [PATCH v3 10/12] MIPS: ath79: Add OF support to the GPIO driver
` [PATCH v3 11/12] of: Add vendor prefix for TP-Link Technologies Co. Ltd
` [PATCH v3 12/12] MIPS: Add basic support for the TL-WR1043ND version 1
[PATH] MIPS: ath79: Add OF support and DTS for TL-WR1043ND
2015-04-24 9:39 UTC (6+ messages)
` [PATCH 02/14] MIPS: ath79: Add basic device tree support
[PATCH] MIPS: asm: asmmacro: Ensure 64-bit FP registers are used with MSA
2015-04-24 7:48 UTC (3+ messages)
[RFC] MIPS: Prevent "BUG: using smp_processor_id() in preemptible..." errors
2015-04-23 21:21 UTC (4+ messages)
[PATCH] MIPS: bcm47xx: Move the BCM47XX board types under a choice symbol
2015-04-23 13:30 UTC (5+ messages)
[PATCH] Revert "MIPS: Provide correct siginfo_t.si_stime"
2015-04-23 11:10 UTC (4+ messages)
[PATCH] MIPS: BCM47XX: Support Luxul XWR-1750 board
2015-04-22 19:58 UTC
[PATCH v3 00/37] JZ4780 & CI20 support
2015-04-22 9:11 UTC (82+ messages)
` [PATCH v3 05/37] MIPS: JZ4740: require & include DT
` [PATCH v3 06/37] MIPS: irq_cpu: declare irqchip table entry
` [PATCH v3 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT
` [PATCH v3 08/37] MIPS: JZ4740: use generic plat_irq_dispatch
` [PATCH v3 09/37] MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c
` [PATCH v3 10/37] devicetree: document Ingenic SoC interrupt controller binding
` [PATCH v3 11/37] MIPS: JZ4740: probe interrupt controller via DT
` [PATCH v3 12/37] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
` [PATCH v3 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller
` [PATCH v3 14/37] MIPS: JZ4740: drop intc debugfs code
` [PATCH v3 15/37] MIPS: JZ4740: remove jz_intc_base global
` [PATCH v3 16/37] MIPS: JZ4740: support >32 interrupts
` [PATCH v3 17/37] MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
` [PATCH v3 18/37] MIPS: JZ4740: read intc base address from DT
` [PATCH v3 19/37] MIPS: JZ4740: avoid JZ4740-specific naming
` [PATCH v3 20/37] MIPS: JZ4740: support newer SoC interrupt controllers
` [PATCH v3 21/37] irqchip: move Ingenic SoC intc driver to drivers/irqchip
` [PATCH v3 22/37] MIPS: JZ4740: call jz4740_clock_init earlier
` [PATCH v3 23/37] MIPS: JZ4740: replace use of jz4740_clock_bdata
` [PATCH v3 24/37] devicetree: add Ingenic CGU binding documentation
` [PATCH v3 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks
` [PATCH v3 26/37] MIPS,clk: migrate JZ4740 to common clock framework
` [PATCH v3 27/37] MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
` [PATCH v3 28/37] MIPS,clk: move jz4740 UDC auto suspend functions "
` [PATCH v3 29/37] MIPS,clk: move jz4740 clock suspend,resume "
` [PATCH v3 30/37] clk: ingenic: add JZ4780 CGU support
` [PATCH v3 31/37] MIPS: JZ4740: remove clock.h
` [PATCH v3 32/37] MIPS: JZ4740: only detect RAM size if not specified in DT
` [PATCH v3 33/37] devicetree: document Ingenic SoC UART binding
` [PATCH v3 34/37] serial: 8250_ingenic: support for Ingenic SoC UARTs
` [PATCH v3 35/37] MIPS: JZ4740: use Ingenic SoC UART driver
` [PATCH v3 36/37] MIPS: ingenic: initial JZ4780 support
` [PATCH v3 37/37] MIPS: ingenic: initial MIPS Creator CI20 support
mips build failures due to commit 8dd928915a73 (mips: fix up obsolete cpu function usage)
2015-04-22 2:59 UTC (6+ messages)
[PATCH V2] MIPS: Loongson: Naming style cleanup and rework
2015-04-22 0:34 UTC (3+ messages)
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