Linux MIPS Architecture development
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 messages from 2026-11-13 19:08:44 to 2026-11-13 23:34:13 UTC [more...]

[PATCH v2 0/3] MIPS: SiByte: Add HW PMU support
 2026-11-13 23:33 UTC  (4+ messages)
` [PATCH v2 1/3] MIPS: SiByte: Wire up the CPU interrupt controller
` [PATCH v2 2/3] MIPS: perf: Add SB1 userspace callchain unwinding
` [PATCH v2 3/3] MIPS: perf: Add SB1 and SB1A performance counter support

[PATCH v6 0/4] MIPS: CI20: Enable SMP with two CPUs
 2026-11-13 21:52 UTC  (6+ messages)
` [PATCH v6 2/4] MIPS: Skip generic IPI setup for platform-specific callbacks
` [PATCH v6 3/4] MIPS: Ingenic: Add XBurst SMP support
` [PATCH v6 4/4] MIPS: CI20: Enable SMP with two CPUs
` (subset) [PATCH v6 0/4] "

[PATCH] MIPS: SiByte: Fix missing function prototypes
 2026-11-13 19:31 UTC  (3+ messages)

[PATCH v2] MIPS: SiByte: Fix missing function prototypes
 2026-11-13 19:19 UTC 


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