Re: RFC: Proper suspend-to-ram implementation of Ingenic SoCs

[Paul Cercueil <paul@crapouillou.net>]

Hi Zhou,

Le jeu., juil. 14 2022 at 12:14:07 +0800, Zhou Yanjie 
<zhouyanjie@wanyeetech.com> a écrit :
> Hi Paul,
> 
> On 2022/7/14 上午4:57, Paul Cercueil wrote:
>> 
>> 
>> Le jeu., juil. 14 2022 at 03:44:34 +0800, Mike Yang 
>> \x7f<reimu@sudomaker.com> a écrit :
>>> Hi Paul,
>>> 
>>> On 7/14/22 00:08, Paul Cercueil wrote:
>>>>  Hi Mike,
>>>>  [...]
>>>> 
>>>>>  If I comment the "wait" instruction, it will exit the suspend 
>>>>> \x7f\x7f\x7f\x7fprocess immediately. And yes, I don't think it suspended 
>>>>> properly.
>>>> 
>>>>  Ok. I was suggesting to try that since it would show if the crash 
>>>> \x7f\x7f\x7fhappens when a particular device gets suspended.
>>>> 
>>>>  Are you certain that your wakeup IRQ is unmasked?
>>> 
>>> I'm not sure. Which register should I check?
>> 
>> Check the IMCR0 / IMCR1 registers. Everything should be masked 
>> except \x7fyour wakeup source. If your wakeup source is a GPIO, also 
>> check that \x7fthe mask register that corresponds to your GPIO.
>> 
> 
> Do you mean ICMR0 and ICMR1 in  the Interrupt Controller?

Yes, sorry.

Cheers,
-Paul

>>>> 
>>>>  [...]
>>>> 
>>>>>>>>   I'm afraid the above didn't work for me. Have you tested 
>>>>>>>> \x7f\x7f\x7f\x7f\x7f\x7f\x7fsuspend-to-ram in person on a X series SoC?
>>>>>> 
>>>>>>   I didn't test on X-series, I mostly work with JZ. But that 
>>>>>> part \x7f\x7f\x7f\x7f\x7fof the design didn't change since the JZ4740.
>>>>>> 
>>>>>>   Cheers,
>>>>>>   -Paul
>>>>>> 
>>>>>> 
>>>>> 
>>>>> 
>>>>>  To be honest, I never owned a board with a JZ series SoC. And 
>>>>> \x7f\x7f\x7f\x7fsorry for assuming the suspend-to-ram is unusable on all 
>>>>> Ingenic \x7f\x7f\x7f\x7fSoCs. IIRC, all the JZ series SoCs have external 
>>>>> DRAM, while the X \x7f\x7f\x7f\x7fseries SoCs have internal DRAM. Also 
>>>>> Ingenic advertised the power \x7f\x7f\x7f\x7fsaving features of the X series 
>>>>> SoCs heavily. Things might be \x7f\x7f\x7f\x7fdifferent since it may involve 
>>>>> additional power management.
>>>> 
>>>>  Even if the 3.x method you were describing works, the currently 
>>>> \x7f\x7f\x7fupstream method should work as well, and if it doesn't, we 
>>>> probably \x7f\x7f\x7fshould try to figure why.
>>>> 
>>>>  I remember doing some tests on the JZ4770 some years ago, and I 
>>>> \x7f\x7f\x7fwould get a power consumption of 7mA when suspended - that's 
>>>> for the \x7f\x7f\x7fwhole board, measured at the 3.7V battery, so about 
>>>> 0.026 W. The \x7f\x7f\x7fonly things powered ON then are the RAM chips and 
>>>> the SoC's RTC module.
>>>> 
>>>>>  At the time of writing the last sentence of the email, Dr. Zhou 
>>>>> \x7f\x7f\x7f\x7fjust pointed out that it may has something to do with the 
>>>>> secure \x7f\x7f\x7f\x7fboot feature introduced in the X series SoC, although 
>>>>> the feature \x7f\x7f\x7f\x7fis not enabled. I already mailed my X1000E & 
>>>>> X1501 boards to Dr. \x7f\x7f\x7f\x7fZhou for further tests. You may want to 
>>>>> get a X1000(E) board (e.g. \x7f\x7f\x7f\x7fhalley2) and test this by yourself.
>>>> 
>>>>  I do have a Cu1000-Neo board, but I have never used it, I 
>>>> wouldn't \x7f\x7f\x7fknow how to test this.
>>>> 
>>>>  Cheers,
>>>>  -Paul
>>>> 
>>>> 
>>> 
>>> Earlier today, Dr. Zhou and I talked to a senior engineer from 
>>> \x7f\x7fIngenic. He said an extra piece of code is necessary for the X 
>>> \x7f\x7fseries, and more CPM registers (other than LPM) are needed to be 
>>> \x7f\x7fconfigured. The X series can't reconfigure the DRAM to exit 
>>> \x7f\x7fself-refresh mode by themselves. He also said, if we really don't 
>>> \x7f\x7fwant to put the code inside the kernel, it's possible to store 
>>> the \x7f\x7f$pc somewhere in the RAM and modify UBoot SPL to do 
>>> additional checks \x7f\x7f(e.g. P0 powerup flag) and jump back to the $pc 
>>> after reconfiguring \x7f\x7fDRAM. I'm not sure if this will work, since 
>>> the core will boot \x7f\x7fstraight from the BROM, and the SFC and/or MSC 
>>> peripherals will be \x7f\x7freconfigured before it can load SPL again 
>>> into the SRAM. It may cause \x7f\x7fconfusion to the kernel SFC/MSC 
>>> drivers. From his words, we can have \x7f\x7fanother method: incorporate 
>>> the code inside UBoot and write it to the \x7f\x7fSRAM prior to booting 
>>> the kernel. What's your opinion?
>> 
>> The X1000 has more CPM registers and do support turning the CPU 
>> \x7fcompletely off, which is new compared to the JZ4780, so that part 
>> is \x7ftrue. However, the regular method to enter SLEEP mode is still 
>> \x7fdescribed in the X1000, X1830 and X2000 programming manuals, and 
>> it's \x7fthe exact same method described in the JZ4780 and even in the 
>> JZ4740 \x7fprogramming manuals. So allow me to doubt.
>> 
>> Knowing that Ingenic's 3.x kernel implements the "complete shutdown" 
>> \x7fsleep mode, I would think that this is why your senior engineer 
>> said \x7fthat an extra piece of code is necessary - because that's how 
>> they \x7fimplemented it. But that does not mean that it is required, 
>> and \x7fnothing in any of the X-series programming manuals suggests 
>> that it is \x7frequired.
>> 
>> Cheers,
>> -Paul
>>