From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D87EC43334 for ; Thu, 7 Jul 2022 09:43:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234973AbiGGJnI (ORCPT ); Thu, 7 Jul 2022 05:43:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233783AbiGGJnH (ORCPT ); Thu, 7 Jul 2022 05:43:07 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9C2A45070; Thu, 7 Jul 2022 02:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1657186985; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i8p03/aknxZm4ISCg5osm/QCfwD06OLWvg98PIGVA6k=; b=4SIGlYDYz6ZeZwMrdFwcHjdodvrTphUWQoqLzkb/6LkauADFI0vWu+8mpxaajfTFhrYj87 UHht/fC++I9qD2m9Mw2oNxWMBu2R3rOFRIB8frxKvS5vDhiJiRJAgBjkfneTYy4BzHYz+t BaW4ijYk24naRuCXPWWhsdjRcMj/ph4= Date: Thu, 07 Jul 2022 10:42:55 +0100 From: Paul Cercueil Subject: Re: [PATCH 08/11] ASoC: jz4740-i2s: Align macro values and sort includes To: Aidan MacDonald Cc: lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: <20220706211330.120198-9-aidanmacdonald.0x0@gmail.com> References: <20220706211330.120198-1-aidanmacdonald.0x0@gmail.com> <20220706211330.120198-9-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Le mer., juil. 6 2022 at 22:13:27 +0100, Aidan MacDonald=20 a =E9crit : > Some purely cosmetic changes: line up all the macro values to > make things easier to read and sort the includes alphabetically. >=20 > Signed-off-by: Aidan MacDonald Acked-by: Paul Cercueil Cheers, -Paul > --- > sound/soc/jz4740/jz4740-i2s.c | 66=20 > +++++++++++++++++------------------ > 1 file changed, 32 insertions(+), 34 deletions(-) >=20 > diff --git a/sound/soc/jz4740/jz4740-i2s.c=20 > b/sound/soc/jz4740/jz4740-i2s.c > index b8d2723c5f90..3a21ee9d34d1 100644 > --- a/sound/soc/jz4740/jz4740-i2s.c > +++ b/sound/soc/jz4740/jz4740-i2s.c > @@ -4,6 +4,9 @@ > */ >=20 > #include > +#include > +#include > +#include > #include > #include > #include > @@ -13,11 +16,6 @@ > #include > #include >=20 > -#include > -#include > - > -#include > - > #include > #include > #include > @@ -35,36 +33,36 @@ > #define JZ_REG_AIC_CLK_DIV 0x30 > #define JZ_REG_AIC_FIFO 0x34 >=20 > -#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) > -#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) > -#define JZ_AIC_CONF_I2S BIT(4) > -#define JZ_AIC_CONF_RESET BIT(3) > -#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) > -#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) > -#define JZ_AIC_CONF_ENABLE BIT(0) > - > -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) > -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) > -#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) > -#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) > -#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) > -#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) > -#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) > +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) > +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) > +#define JZ_AIC_CONF_I2S BIT(4) > +#define JZ_AIC_CONF_RESET BIT(3) > +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) > +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) > +#define JZ_AIC_CONF_ENABLE BIT(0) > + > +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) > +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) > +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) > +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) > +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) > +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) > +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) > #define JZ_AIC_CTRL_FLUSH BIT(8) > -#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) > -#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) > -#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) > -#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) > -#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) > -#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) > -#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) > - > -#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) > -#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) > -#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) > -#define JZ_AIC_I2S_FMT_MSB BIT(0) > - > -#define JZ_AIC_I2S_STATUS_BUSY BIT(2) > +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) > +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) > +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) > +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) > +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) > +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) > +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) > + > +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) > +#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) > +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) > +#define JZ_AIC_I2S_FMT_MSB BIT(0) > + > +#define JZ_AIC_I2S_STATUS_BUSY BIT(2) >=20 > struct i2s_soc_info { > struct snd_soc_dai_driver *dai; > -- > 2.35.1 >=20