Re: [PATCH v7 2/5] mips: bmips: rework and cache CBR addr handling

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Tue, Jun 11, 2024 at 01:35:34PM +0200, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
> 
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
> 
> bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with
> legacy brcm47xx/brcm63xx and generic BMIPS target.
> 
> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  arch/mips/bcm47xx/prom.c      | 3 +++
>  arch/mips/bcm63xx/prom.c      | 3 +++
>  arch/mips/bmips/dma.c         | 2 +-
>  arch/mips/bmips/setup.c       | 4 +++-
>  arch/mips/include/asm/bmips.h | 1 +
>  arch/mips/kernel/smp-bmips.c  | 6 ++++--
>  6 files changed, 15 insertions(+), 4 deletions(-)

still problems on a bcm47xx build:

mips64-linux-gnu-ld: arch/mips/bcm47xx/prom.o: in function `prom_init':
/local/tbogendoerfer/korg/linux/arch/mips/bcm47xx/prom.c:(.init.text+0x3c): undefined reference to `bmips_cbr_addr'
mips64-linux-gnu-ld: /local/tbogendoerfer/korg/linux/arch/mips/bcm47xx/prom.c:(.init.text+0x44): undefined reference to `bmips_cbr_addr'

Thomas.

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