From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD3CB1B4C58 for ; Thu, 29 Aug 2024 17:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724952811; cv=none; b=iDQdTMxdcLRvTML9v3D73u6BH4jho0ta9WqmFWYeW7vKwYXBW+BiBXfcvs9FNoH4acn7e5nWw8pSIb5fDK4kty4Dug0WnEboi+icA4Dq+aOyjuX6l1ojpkyF/leJF4KBA5iW8WUCD4fwKLZx1BwtA8IG4HXQIfySJ7NlBVpQBSU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724952811; c=relaxed/simple; bh=xq019WSbU/+BH2MTqfSQdLA7OMmY7hhfvIXVLV7r5gw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Vsdu8Vcsbqxm5I92AZJ2wbQ7kn3rpT6eiuH93e+/pddyTaiwD9ezgQZ38IMk8pO3LsXzp+J7kJuSf24dQmBDm5xzu/BrHQVoojphJVyPyWj7U44Ans+hzjt0CNGRsNKpOYO3yE23BnNxXR8zF1S4w+b3bVsiefWr+UNQOY4MQN4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=qyZUgth2; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="qyZUgth2" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-7ae3d7222d4so627497a12.3 for ; Thu, 29 Aug 2024 10:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724952809; x=1725557609; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=ShOV+xhv6/I7AhDzzz24YoQnvepxBGugrDU9V6pmXjY=; b=qyZUgth2dly3nMWS8qXjdxaDbdECPTmlyUQ1VrybCYw6A8/eT0YKVOMybRt52K2AlX 8fDy5AD1LmEYw3+rVhuawDZyraBlZMCKUuIZWZ1Mjd+iiXKpLY444eIQd4U/19Tzm93A I2cQQD8YXKzH6pNUBmQDDqYgKWKU91aMJXmc+R3wxL/d4XYTu/ftEzmRHERrZpSYsc+H 4EqHFdhj0G0TI2LzKEwdxqHIhYmd3s4BEh1k9xoLa506EIBuDgaXrMTe9FcOIZe1EFF/ slCQ789BQWSVmH3nkHR2t5U+6SkwFEAN3v1PDl/JfywwsWmea+FgjeveM3ZpSjDHpcJH U5rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724952809; x=1725557609; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ShOV+xhv6/I7AhDzzz24YoQnvepxBGugrDU9V6pmXjY=; b=VPDxf/Ff/OxfiQFQuHHXqLVp63v2FafXaoJ89aYHT4wUvEfBw0hagsqZURF0Yv3oNV GGov+4pTUoalDTyZoBTcENqwibwEz38Grb9xXPFY8HJqDXD8IxwcpZUZb9+cnXwXZo0a QZYc6jPJiM19to3K++alBQyYkDOIvWWH0RRou6Ab+GY9Ze5gWyvXmCZXYMHQc32+ke0j j6loEoMtrPewx5/CjnLYys+c0DGGkvNAH3N8RcdtZJb0c9lLX2ibl8SntbYIZ5+pP6zW aWCBH9tWYXkRvzYc9qkoHwZAnVck2gZ7sLwLdMnA2BiHAZs5dK/YZc91Kt/4RWzEur5C yheg== X-Forwarded-Encrypted: i=1; AJvYcCXHtqRuu3zPYbAaJrxkPFeQloPs9mJzXtaLfuOBwGeHJyfWLXj/u7Z8NWkm6Iq82XTlqhAUZ9iQh9Or@vger.kernel.org X-Gm-Message-State: AOJu0YxSEuyD1Vu/AzXcgJPQW5K84VxpB5LSOoCP5aBien/IP3TZEdlt DXyz/9oa1OWoGL0ouHg5rP3LBi7D45pN2MSRngdOplKdne/a3oS/h0aRKv0DqvM= X-Google-Smtp-Source: AGHT+IEMMPSZiUHtBfNuQb92KkzHdlzWvSIVDrDVVbnqmIDING28StXdegl4Q9VHUGwvTGBDq12VFQ== X-Received: by 2002:a17:90b:524a:b0:2d3:90e1:41c7 with SMTP id 98e67ed59e1d1-2d85638414emr3575500a91.31.1724952808963; Thu, 29 Aug 2024 10:33:28 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:c81:fe51:78cb:fc02]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d85b0fdf44sm1949050a91.6.2024.08.29.10.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2024 10:33:28 -0700 (PDT) Date: Thu, 29 Aug 2024 10:33:22 -0700 From: Charlie Jenkins To: Michal Hocko Cc: Arnd Bergmann , Richard Henderson , Ivan Kokshaysky , Matt Turner , Vineet Gupta , Russell King , Guo Ren , Huacai Chen , WANG Xuerui , Thomas Bogendoerfer , "James E.J. Bottomley" , Helge Deller , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Naveen N Rao , Alexander Gordeev , Gerald Schaefer , Heiko Carstens , Vasily Gorbik , Christian Borntraeger , Sven Schnelle , Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , "David S. Miller" , Andreas Larsson , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Muchun Song , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Shuah Khan , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH RFC v2 0/4] mm: Introduce MAP_BELOW_HINT Message-ID: References: <20240829-patches-below_hint_mmap-v2-0-638a28d9eae0@rivosinc.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Aug 29, 2024 at 10:30:56AM +0200, Michal Hocko wrote: > On Thu 29-08-24 00:15:57, Charlie Jenkins wrote: > > Some applications rely on placing data in free bits addresses allocated > > by mmap. Various architectures (eg. x86, arm64, powerpc) restrict the > > address returned by mmap to be less than the 48-bit address space, > > unless the hint address uses more than 47 bits (the 48th bit is reserved > > for the kernel address space). > > > > The riscv architecture needs a way to similarly restrict the virtual > > address space. On the riscv port of OpenJDK an error is thrown if > > attempted to run on the 57-bit address space, called sv57 [1]. golang > > has a comment that sv57 support is not complete, but there are some > > workarounds to get it to mostly work [2]. > > > > These applications work on x86 because x86 does an implicit 47-bit > > restriction of mmap() address that contain a hint address that is less > > than 48 bits. > > > > Instead of implicitly restricting the address space on riscv (or any > > current/future architecture), a flag would allow users to opt-in to this > > behavior rather than opt-out as is done on other architectures. This is > > desirable because it is a small class of applications that do pointer > > masking. > > IIRC this has been discussed at length when 5-level page tables support > has been proposed for x86. Sorry I do not have a link handy but lore > should help you. Linus was not really convinced and in the end vetoed it > and prefer that those few applications that benefit from greater address > space would do that explicitly than other way around. I believe I found the conversation you were referring to. Ingo Molnar recommended a flag similar to what I have proposed [1]. Catalin recommended to make 52-bit opt-in on arm64 [2]. Dave Hansen brought up MPX [3]. However these conversations are tangential to what I am proposing. arm64 and x86 decided to have the default address space be 48 bits. However this was done on a per-architecture basis with no way for applications to have guarantees between architectures. Even this behavior to restrict to 48 bits does not even appear in the man pages, so would require reading the kernel source code to understand that this feature is available. Then to opt-in to larger address spaces, applications have to know to provide a hint address that is greater than 47 bits, mmap() will then return an address that contains up to 56 bits on x86 and 52 bits on arm64. This difference of 4 bits causes inconsistency and is part of the problem I am trying to solve with this flag. I am not proposing to change x86 and arm64 away from using their opt-out feature, I am instead proposing a standard ABI for applications that need some guarantees of the bits used in pointers. - Charlie Link: https://lore.kernel.org/lkml/20161209050130.GC2595@gmail.com/ [1] Link: https://lore.kernel.org/lkml/20161209105120.GA3705@e104818-lin.cambridge.arm.com/ [2] Link: https://lore.kernel.org/lkml/a2f86495-b55f-fda0-40d2-242c45d3c1f3@intel.com/ [3] > > -- > Michal Hocko > SUSE Labs