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[88.10.102.251]) by smtp.gmail.com with ESMTPSA id f197sm27108349wme.22.2019.09.01.16.04.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Sep 2019 16:04:45 -0700 (PDT) Subject: Re: [PATCH 020/120] MIPS: R5900: Define CP0.Config register fields To: Fredrik Noring , linux-mips@vger.kernel.org References: From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: url=http://pgp.mit.edu/pks/lookup?op=get&search=0xE3E32C2CDEADC0DE Message-ID: Date: Mon, 2 Sep 2019 01:04:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On 9/1/19 5:43 PM, Fredrik Noring wrote: > The following CP0.Config fields are specific to the R5900[1]: > > Field | Bit | Type | Description > ------+-----+------+----------------------------- > DIE | 18 | RW | Enable double issue > ICE | 17 | RW | Enable the instruction cache > DCE | 16 | RW | Enable the data cache > BE | 15 | RO | Enable big-endian > NBE | 13 | RW | Enable nonblocking load > BPE | 12 | RW | Enable branch prediction > ------+-----+------+----------------------------- > > References: > > [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, > Toshiba Corporation, p. 4-23, https://wiki.qemu.org/File:C790.pdf > > Signed-off-by: Fredrik Noring > --- > arch/mips/include/asm/mipsregs.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h > index ec22406c800f..a3b3ee011539 100644 > --- a/arch/mips/include/asm/mipsregs.h > +++ b/arch/mips/include/asm/mipsregs.h > @@ -511,6 +511,14 @@ > #define R5K_CONF_SE (_ULCAST_(1) << 12) > #define R5K_CONF_SS (_ULCAST_(3) << 20) > > +/* Bits specific to the R5900. */ > +#define R5900_CONF_BPE (_ULCAST_(1) << 12) /* Enable branch prediction. */ > +#define R5900_CONF_NBE (_ULCAST_(1) << 13) /* Enable non-blocking load. */ > +#define R5900_CONF_BE (_ULCAST_(1) << 15) /* Enable big-endian (read-only). */ > +#define R5900_CONF_DCE (_ULCAST_(1) << 16) /* Enable the data cache. */ > +#define R5900_CONF_ICE (_ULCAST_(1) << 17) /* Enable the instruction cache. */ > +#define R5900_CONF_DIE (_ULCAST_(1) << 18) /* Enable double issue. */ > + > /* Bits specific to the RM7000. */ > #define RM7K_CONF_SE (_ULCAST_(1) << 3) > #define RM7K_CONF_TE (_ULCAST_(1) << 12) > Reviewed-by: Philippe Mathieu-Daudé