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Wed, 11 Mar 2026 12:44:55 -0700 (PDT) X-Received: by 2002:a05:6820:468b:b0:67a:47b:5a1a with SMTP id 006d021491bc7-67bc8a92d45mr2060493eaf.65.1773258294899; Wed, 11 Mar 2026 12:44:54 -0700 (PDT) Received: from redhat.com ([2600:382:7704:370d:c6a3:6b0f:aa31:6ca2]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-67bc8efb85esm1894481eaf.1.2026.03.11.12.44.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 12:44:54 -0700 (PDT) Date: Wed, 11 Mar 2026 15:44:50 -0400 From: Brian Masney To: Caleb James DeLisle Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu Message-ID: References: <20260309131818.74467-1-cjd@cjdns.fr> <20260309131818.74467-3-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) On Wed, Mar 11, 2026 at 06:12:59PM +0100, Caleb James DeLisle wrote: > Hello Brian, > > Thank you for taking the time! > > > On 11/03/2026 15:39, Brian Masney wrote: > > Hi Caleb, > > > > On Mon, Mar 09, 2026 at 01:18:12PM +0000, Caleb James DeLisle wrote: > > > EcoNet EN751221 clock/reset driver is significantly similar to the > > > EN7523 / EN7581, however the EN751221 does not have a neat batch of clock > > > divider registers so there are fewer known clocks, and the frequency of > > > each clock is derived differently. This clock driver will probably work > > > correctly on EN751627, EN7528, and EN7580. > > > > > > Signed-off-by: Caleb James DeLisle > > > --- > > > static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) > > > { > > > @@ -604,7 +703,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev, > > > en7523_register_clocks(&pdev->dev, clk_data, base, np_base); > > > return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map, > > > - ARRAY_SIZE(en7523_rst_map)); > > > + ARRAY_SIZE(en7523_rst_map), > > > + en7581_rst_ofs); > > I assume the mix of en7523 and en7581 is ok here? > > > Correct, en7581 came first, then when en7523 was added they reused the > function. I'm only changing the offsets to be passed in because en751221 has > more reset registers so different offset table than the others. Sounds good. I just wanted to confirm. > > > + else > > > + clk_data->hws[key] = hw; > > Should the error code be returned here? I know the function has try in > > it's name, however if this fails, then it still registers it. > > > This function follows the general pattern of en7581_register_clocks(). If a > clock can't be registered, leave clk_data->hws[key] as NULL, log, and > continue. There's only two possible reasons for failing, if > clk_hw_register_fixed_rate() fails then it's not registered because it > failed. If key >= EN751221_MAX_CLKS, it does register but I'll fix this so > it's checking that before clk_hw_register_fixed_rate(). I see that Stephen picked up this driver in 2022 with that behavior. I'm fine with it if he is. > > > + /* BUS */ > > > + rate = FIELD_GET(EN751221_REG_BUS_MASK, > > > + readl(np_base + EN751221_REG_BUS)); > > > + rate *= 1000000; > > > + en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus", > > > + rate); > > > + > > > + /* CPU */ > > > + en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu", > > > + rate * 4); > > > + > > > + /* HPT */ > > > + switch (hid) { > > > + case HIR_EN751221: > > > + case HIR_EN751627: > > > + case HIR_EN7526C: > > > + case HIR_EN7580: > > > + case HIR_EN7528: > > > + rate = 200000000; > > > + break; > > > + case HIR_MT7505: > > > + rate = 100000000; > > > + break; > > > + case HIR_MT751020: > > > + rate = 800000000 / 3; > > > + break; > > > + default: > > > + rate = 250000000; > > Should a warning be logged here or in get_hw_id() above? hid can be set > > to HIR_UNKNOWN here. > > Now that I'm looking at this again, I'm starting to think it might be better > to just remove it and use a fixed-clock in the DT. I wrote it aiming for > completeness, but this particular clock has so much code supporting it, I'm > feeling like it just doesn't make any sense. > > Let me know if you have a feeling on this because I'm swaying in the > direction of just re-sending with it removed. That makes sense to me. Brian