[PATCH] MIPS: SiByte: Bring back cache initialisation

[PATCH] MIPS: SiByte: Bring back cache initialisation

[Maciej W. Rozycki]

Bring back cache initialisation for Broadcom SiByte SB1 cores, which has 
been removed causing the kernel to hang at bootstrap right after:

Dentry cache hash table entries: 524288 (order: 8, 4194304 bytes, linear)
Inode-cache hash table entries: 262144 (order: 7, 2097152 bytes, linear)

The cause of the problem is R4k cache handlers are also used by Broadcom 
SiByte SB1 cores, however with a different cache error exception handler 
and therefore not using CPU_R4K_CACHE_TLB:

obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_SB1)           += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o

(from arch/mips/mm/Makefile).

Fixes: bbe4f634f48c ("mips: fix r3k_cache_init build regression")
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Cc: stable@vger.kernel.org # v6.8+
---
 arch/mips/mm/cache.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

linux-mips-sibyte-r4k-cache-init.diff
Index: linux-swarm64/arch/mips/mm/cache.c
===================================================================
--- linux-swarm64.orig/arch/mips/mm/cache.c
+++ linux-swarm64/arch/mips/mm/cache.c
@@ -207,7 +207,8 @@ void cpu_cache_init(void)
 {
 	if (IS_ENABLED(CONFIG_CPU_R3000) && cpu_has_3k_cache)
 		r3k_cache_init();
-	if (IS_ENABLED(CONFIG_CPU_R4K_CACHE_TLB) && cpu_has_4k_cache)
+	if ((IS_ENABLED(CONFIG_CPU_R4K_CACHE_TLB) ||
+	     IS_ENABLED(CONFIG_CPU_SB1)) && cpu_has_4k_cache)
 		r4k_cache_init();
 
 	if (IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON) && cpu_has_octeon_cache)

Re: [PATCH] MIPS: SiByte: Bring back cache initialisation

[Thomas Bogendoerfer]

On Fri, Mar 27, 2026 at 11:38:06AM +0000, Maciej W. Rozycki wrote:
> Bring back cache initialisation for Broadcom SiByte SB1 cores, which has 
> been removed causing the kernel to hang at bootstrap right after:
> 
> Dentry cache hash table entries: 524288 (order: 8, 4194304 bytes, linear)
> Inode-cache hash table entries: 262144 (order: 7, 2097152 bytes, linear)
> 
> The cause of the problem is R4k cache handlers are also used by Broadcom 
> SiByte SB1 cores, however with a different cache error exception handler 
> and therefore not using CPU_R4K_CACHE_TLB:
> 
> obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
> obj-$(CONFIG_CPU_SB1)           += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
> 
> (from arch/mips/mm/Makefile).
> 
> Fixes: bbe4f634f48c ("mips: fix r3k_cache_init build regression")
> Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
> Cc: stable@vger.kernel.org # v6.8+
> ---
>  arch/mips/mm/cache.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> linux-mips-sibyte-r4k-cache-init.diff
> Index: linux-swarm64/arch/mips/mm/cache.c
> ===================================================================
> --- linux-swarm64.orig/arch/mips/mm/cache.c
> +++ linux-swarm64/arch/mips/mm/cache.c
> @@ -207,7 +207,8 @@ void cpu_cache_init(void)
>  {
>  	if (IS_ENABLED(CONFIG_CPU_R3000) && cpu_has_3k_cache)
>  		r3k_cache_init();
> -	if (IS_ENABLED(CONFIG_CPU_R4K_CACHE_TLB) && cpu_has_4k_cache)
> +	if ((IS_ENABLED(CONFIG_CPU_R4K_CACHE_TLB) ||
> +	     IS_ENABLED(CONFIG_CPU_SB1)) && cpu_has_4k_cache)
>  		r4k_cache_init();
>  
>  	if (IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON) && cpu_has_octeon_cache)

applied to mips-fixes

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]