Re: [PATCH 0/3] MIPS: Avoid a TLB shutdown induced by a hidden TLB entry bit

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Fri, Mar 27, 2026 at 06:57:10PM +0000, Maciej W. Rozycki wrote:
> Hi,
> 
>  This is a reimplementation of initial TLB entry uniquification so as to 
> address an issue with processors that implement a hidden TLB entry bit 
> triggered by commit 9f048fa48740 ("MIPS: mm: Prevent a TLB shutdown on 
> initial uniquification") for platforms that hand the TLB over unchanged 
> from reset.
> 
>  This has been verified across the following systems:
> 
> - DECstation 5000/150, R4000SC MIPS III CPU, SEGBITS == 40, 48-entry TLB, 
>   32-bit kernel,
> 
> - Broadcom BCM91250A, BCM1250 MIPS64 CPU, SEGBITS == 44, 64-entry TLB, 
>   64-bit kernel,
> 
> - MIPS Malta, 74Kf MIPS32r2 CPU, SEGBITS == 31, 64-entry TLB, 32-bit 
>   kernel.
> 
> A debug change was used to verify the TLB is initialised as expected.
> 
>  See individual commit descriptions for details.
> 
>  I consider this code ready to use, but given the diversity of TLB designs 
> with MIPS architecture processors I will appreciate verification across 
> various actual hardware, particularly in preparation for backporting, as 
> this addresses a serious regression for a subset of systems.
> 
>  Please apply otherwise.  Thank you for patience waiting for this fix.

series applied to mips-fixes

Thomas.

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